5637 lines
65 KiB
Plaintext
5637 lines
65 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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|
unitName "numeric_std"
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itemName "ALL"
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|
)
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]
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|
instances [
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|
(Instance
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name "I1"
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duLibraryName "Curves_test"
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duName "beamerPeriphBlanking_tester"
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elements [
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]
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mwi 0
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|
uid 421,0
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)
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|
(Instance
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|
name "I3"
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|
duLibraryName "Curves"
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duName "lowpass"
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|
elements [
|
|
(GiElement
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|
name "signalBitNb"
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|
type "positive"
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|
value "signalBitNb"
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|
)
|
|
(GiElement
|
|
name "shiftBitNb"
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|
type "positive"
|
|
value "8"
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|
)
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|
]
|
|
mwi 0
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|
uid 984,0
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)
|
|
(Instance
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|
name "I0"
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duLibraryName "Curves"
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duName "beamerPeriphBlanking"
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|
elements [
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|
(GiElement
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name "dataBitNb"
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|
type "positive"
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|
value "16"
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)
|
|
(GiElement
|
|
name "addressBitNb"
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|
type "positive"
|
|
value "24"
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|
)
|
|
]
|
|
mwi 0
|
|
uid 1599,0
|
|
)
|
|
(Instance
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|
name "I2"
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|
duLibraryName "Curves_test"
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|
duName "DAC_5543"
|
|
elements [
|
|
]
|
|
mwi 0
|
|
uid 1624,0
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|
)
|
|
(Instance
|
|
name "I4"
|
|
duLibraryName "Curves_test"
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|
duName "DAC_5543"
|
|
elements [
|
|
]
|
|
mwi 0
|
|
uid 1649,0
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)
|
|
]
|
|
embeddedInstances [
|
|
(EmbeddedInstance
|
|
name "eb2"
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number "2"
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)
|
|
]
|
|
libraryRefs [
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|
"ieee"
|
|
]
|
|
)
|
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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|
VExpander (VariableExpander
|
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vvMap [
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|
(vvPair
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variable " "
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|
value " "
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|
)
|
|
(vvPair
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|
variable "HDLDir"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
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|
)
|
|
(vvPair
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|
variable "HDSDir"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
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)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
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|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
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|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb"
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|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerPeriphBlanking_tb"
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|
)
|
|
(vvPair
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|
variable "date"
|
|
value "28.04.2023"
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|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
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|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "beamerPeriphBlanking_tb"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
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|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:05:23"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
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|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip_test"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip_test"
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|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "beamerPeriphBlanking_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerPeriphBlanking_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:05:23"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "beamerPeriphBlanking_tb"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
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|
)
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LanguageMgr "Vhdl2008LangMgr"
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uid 153,0
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optionalChildren [
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decl (Decl
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decl (Decl
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xt "2000,36600,15800,37600"
|
|
st "SIGNAL selSinCos : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*42 (Net
|
|
uid 1477,0
|
|
decl (Decl
|
|
n "outZ"
|
|
t "std_ulogic"
|
|
o 18
|
|
suid 15,0
|
|
)
|
|
declText (MLText
|
|
uid 1478,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,33600,15300,34600"
|
|
st "SIGNAL outZ : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*43 (SaComponent
|
|
uid 1599,0
|
|
optionalChildren [
|
|
*44 (CptPort
|
|
uid 1519,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1520,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,31625,49000,32375"
|
|
)
|
|
tg (CPTG
|
|
uid 1521,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1522,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,31400,53400,32600"
|
|
st "clock"
|
|
blo "50000,32400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
)
|
|
)
|
|
)
|
|
*45 (CptPort
|
|
uid 1523,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1524,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,5625,49000,6375"
|
|
)
|
|
tg (CPTG
|
|
uid 1525,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1526,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,5400,52900,6600"
|
|
st "addr"
|
|
blo "50000,6400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "addr"
|
|
t "unsigned"
|
|
b "(addressBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
*46 (CptPort
|
|
uid 1527,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1528,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,5625,65750,6375"
|
|
)
|
|
tg (CPTG
|
|
uid 1529,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1530,0
|
|
va (VaSet
|
|
)
|
|
xt "61001,5400,64001,6600"
|
|
st "outX"
|
|
ju 2
|
|
blo "64001,6400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*47 (CptPort
|
|
uid 1531,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1532,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,33625,49000,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 1533,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1534,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,33400,53300,34600"
|
|
st "reset"
|
|
blo "50000,34400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
)
|
|
)
|
|
)
|
|
*48 (CptPort
|
|
uid 1535,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1536,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,7625,65750,8375"
|
|
)
|
|
tg (CPTG
|
|
uid 1537,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1538,0
|
|
va (VaSet
|
|
)
|
|
xt "61001,7400,64001,8600"
|
|
st "outY"
|
|
ju 2
|
|
blo "64001,8400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 5
|
|
)
|
|
)
|
|
)
|
|
*49 (CptPort
|
|
uid 1539,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1540,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,7625,49000,8375"
|
|
)
|
|
tg (CPTG
|
|
uid 1541,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1542,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,7400,54000,8600"
|
|
st "dataIn"
|
|
blo "50000,8400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
)
|
|
)
|
|
)
|
|
*50 (CptPort
|
|
uid 1543,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1544,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,13625,49000,14375"
|
|
)
|
|
tg (CPTG
|
|
uid 1545,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1546,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,13400,51700,14600"
|
|
st "rd"
|
|
blo "50000,14400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "rd"
|
|
t "std_ulogic"
|
|
o 7
|
|
)
|
|
)
|
|
)
|
|
*51 (CptPort
|
|
uid 1547,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1548,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,15625,49000,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 1549,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1550,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,15400,52600,16600"
|
|
st "wrH"
|
|
blo "50000,16400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "wrH"
|
|
t "std_ulogic"
|
|
o 8
|
|
)
|
|
)
|
|
)
|
|
*52 (CptPort
|
|
uid 1551,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1552,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,19625,49000,20375"
|
|
)
|
|
tg (CPTG
|
|
uid 1553,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1554,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,19400,51900,20600"
|
|
st "cs"
|
|
blo "50000,20400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "cs"
|
|
t "std_ulogic"
|
|
o 9
|
|
)
|
|
)
|
|
)
|
|
*53 (CptPort
|
|
uid 1555,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1556,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,17625,49000,18375"
|
|
)
|
|
tg (CPTG
|
|
uid 1557,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1558,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,17400,52400,18600"
|
|
st "wrL"
|
|
blo "50000,18400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "wrL"
|
|
t "std_ulogic"
|
|
o 10
|
|
)
|
|
)
|
|
)
|
|
*54 (CptPort
|
|
uid 1559,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1560,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48250,9625,49000,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 1561,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1562,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,9400,54800,10600"
|
|
st "dataOut"
|
|
blo "50000,10400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_logic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 11
|
|
)
|
|
)
|
|
)
|
|
*55 (CptPort
|
|
uid 1563,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1564,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,31625,65750,32375"
|
|
)
|
|
tg (CPTG
|
|
uid 1565,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1566,0
|
|
va (VaSet
|
|
)
|
|
xt "59401,31400,64001,32600"
|
|
st "testOut"
|
|
ju 2
|
|
blo "64001,32400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO 16)"
|
|
o 12
|
|
)
|
|
)
|
|
)
|
|
*56 (CptPort
|
|
uid 1567,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1568,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,29625,65750,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 1569,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1570,0
|
|
va (VaSet
|
|
)
|
|
xt "58201,29400,64001,30600"
|
|
st "selSinCos"
|
|
ju 2
|
|
blo "64001,30400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 13
|
|
)
|
|
)
|
|
)
|
|
*57 (CptPort
|
|
uid 1571,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1572,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,9625,65750,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 1573,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1574,0
|
|
va (VaSet
|
|
)
|
|
xt "61001,9400,64001,10600"
|
|
st "outZ"
|
|
ju 2
|
|
blo "64001,10400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outZ"
|
|
t "std_ulogic"
|
|
o 14
|
|
)
|
|
)
|
|
)
|
|
*58 (CptPort
|
|
uid 1575,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1576,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,15625,65750,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 1577,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1578,0
|
|
va (VaSet
|
|
)
|
|
xt "59900,15400,64000,16600"
|
|
st "CLK_X"
|
|
ju 2
|
|
blo "64000,16400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CLK_X"
|
|
t "std_ulogic"
|
|
o 17
|
|
)
|
|
)
|
|
)
|
|
*59 (CptPort
|
|
uid 1579,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1580,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,13625,65750,14375"
|
|
)
|
|
tg (CPTG
|
|
uid 1581,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1582,0
|
|
va (VaSet
|
|
)
|
|
xt "59300,13400,64000,14600"
|
|
st "CS_X_n"
|
|
ju 2
|
|
blo "64000,14400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CS_X_n"
|
|
t "std_ulogic"
|
|
o 15
|
|
)
|
|
)
|
|
)
|
|
*60 (CptPort
|
|
uid 1583,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1584,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,17625,65750,18375"
|
|
)
|
|
tg (CPTG
|
|
uid 1585,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1586,0
|
|
va (VaSet
|
|
)
|
|
xt "60000,17400,64000,18600"
|
|
st "SDI_X"
|
|
ju 2
|
|
blo "64000,18400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "SDI_X"
|
|
t "std_ulogic"
|
|
o 16
|
|
)
|
|
)
|
|
)
|
|
*61 (CptPort
|
|
uid 1587,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1588,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,21625,65750,22375"
|
|
)
|
|
tg (CPTG
|
|
uid 1589,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1590,0
|
|
va (VaSet
|
|
)
|
|
xt "59300,21400,64000,22600"
|
|
st "CS_Y_n"
|
|
ju 2
|
|
blo "64000,22400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CS_Y_n"
|
|
t "std_ulogic"
|
|
o 19
|
|
)
|
|
)
|
|
)
|
|
*62 (CptPort
|
|
uid 1591,0
|
|
ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 1592,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
|
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)
|
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xt "65000,25625,65750,26375"
|
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)
|
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tg (CPTG
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|
uid 1593,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
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uid 1594,0
|
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va (VaSet
|
|
)
|
|
xt "60000,25400,64000,26600"
|
|
st "SDI_Y"
|
|
ju 2
|
|
blo "64000,26400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "SDI_Y"
|
|
t "std_ulogic"
|
|
o 20
|
|
)
|
|
)
|
|
)
|
|
*63 (CptPort
|
|
uid 1595,0
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ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 1596,0
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ro 90
|
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va (VaSet
|
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vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "65000,23625,65750,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 1597,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1598,0
|
|
va (VaSet
|
|
)
|
|
xt "59900,23400,64000,24600"
|
|
st "CLK_Y"
|
|
ju 2
|
|
blo "64000,24400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CLK_Y"
|
|
t "std_ulogic"
|
|
o 18
|
|
)
|
|
)
|
|
)
|
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]
|
|
shape (Rectangle
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uid 1600,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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bg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
|
|
)
|
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xt "49000,2000,65000,36000"
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)
|
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oxt "0,0,8000,10000"
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ttg (MlTextGroup
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uid 1601,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 1602,0
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va (VaSet
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)
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xt "49600,35800,53900,37000"
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st "Curves"
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blo "49600,36800"
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tm "BdLibraryNameMgr"
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)
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*65 (Text
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uid 1603,0
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va (VaSet
|
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)
|
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xt "49600,36800,62900,38000"
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st "beamerPeriphBlanking"
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blo "49600,37800"
|
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tm "CptNameMgr"
|
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)
|
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*66 (Text
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uid 1604,0
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va (VaSet
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)
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xt "49600,37800,51500,39000"
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st "I0"
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blo "49600,38800"
|
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tm "InstanceNameMgr"
|
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)
|
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]
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)
|
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ga (GenericAssociation
|
|
uid 1605,0
|
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ps "EdgeToEdgeStrategy"
|
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matrix (Matrix
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uid 1606,0
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text (MLText
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uid 1607,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "49000,39600,64000,41600"
|
|
st "dataBitNb = 16 ( positive )
|
|
addressBitNb = 24 ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
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elements [
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(GiElement
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|
name "dataBitNb"
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|
type "positive"
|
|
value "16"
|
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)
|
|
(GiElement
|
|
name "addressBitNb"
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type "positive"
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|
value "24"
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)
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]
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)
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ordering 1
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portVis (PortSigDisplay
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sTC 0
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)
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archFileType "UNKNOWN"
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)
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*67 (SaComponent
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uid 1624,0
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optionalChildren [
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*68 (CptPort
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uid 1608,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1609,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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|
)
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xt "106250,32625,107000,33375"
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)
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tg (CPTG
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uid 1610,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 1611,0
|
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va (VaSet
|
|
)
|
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xt "108000,32400,110800,33600"
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|
st "CLK"
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|
blo "108000,33400"
|
|
)
|
|
)
|
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thePort (LogicalPort
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decl (Decl
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n "CLK"
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t "std_ulogic"
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o 17
|
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)
|
|
)
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)
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*69 (CptPort
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uid 1612,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1613,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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|
)
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xt "106250,28625,107000,29375"
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)
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tg (CPTG
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uid 1614,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 1615,0
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va (VaSet
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)
|
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xt "108000,28400,111400,29600"
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|
st "CS_n"
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blo "108000,29400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
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|
decl (Decl
|
|
n "CS_n"
|
|
t "std_ulogic"
|
|
o 15
|
|
)
|
|
)
|
|
)
|
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*70 (CptPort
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|
uid 1616,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1617,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "106250,30625,107000,31375"
|
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)
|
|
tg (CPTG
|
|
uid 1618,0
|
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ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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f (Text
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|
uid 1619,0
|
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va (VaSet
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)
|
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xt "108000,30400,110700,31600"
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|
st "SDI"
|
|
blo "108000,31400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "SDI"
|
|
t "std_ulogic"
|
|
o 16
|
|
)
|
|
)
|
|
)
|
|
*71 (CptPort
|
|
uid 1620,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1621,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "115000,28625,115750,29375"
|
|
)
|
|
tg (CPTG
|
|
uid 1622,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1623,0
|
|
va (VaSet
|
|
)
|
|
xt "111200,28400,114000,29600"
|
|
st "Iout"
|
|
ju 2
|
|
blo "114000,29400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "Iout"
|
|
t "natural"
|
|
o 4
|
|
)
|
|
)
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|
)
|
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]
|
|
shape (Rectangle
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uid 1625,0
|
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va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
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|
lineWidth 2
|
|
)
|
|
xt "107000,27000,115000,35000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
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ttg (MlTextGroup
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|
uid 1626,0
|
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ps "CenterOffsetStrategy"
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|
stg "VerticalLayoutStrategy"
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textVec [
|
|
*72 (Text
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|
uid 1627,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,34800,115200,36000"
|
|
st "Curves_test"
|
|
blo "107600,35800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*73 (Text
|
|
uid 1628,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,35800,114100,37000"
|
|
st "DAC_5543"
|
|
blo "107600,36800"
|
|
tm "CptNameMgr"
|
|
)
|
|
*74 (Text
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|
uid 1629,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,36800,109500,38000"
|
|
st "I2"
|
|
blo "107600,37800"
|
|
tm "InstanceNameMgr"
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|
)
|
|
]
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)
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ga (GenericAssociation
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|
uid 1630,0
|
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ps "EdgeToEdgeStrategy"
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|
matrix (Matrix
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uid 1631,0
|
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text (MLText
|
|
uid 1632,0
|
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va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "72000,12000,72000,12000"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
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)
|
|
portVis (PortSigDisplay
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|
)
|
|
archFileType "UNKNOWN"
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)
|
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*75 (SaComponent
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uid 1649,0
|
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optionalChildren [
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*76 (CptPort
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uid 1658,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1659,0
|
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ro 90
|
|
va (VaSet
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vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "106250,48625,107000,49375"
|
|
)
|
|
tg (CPTG
|
|
uid 1660,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 1661,0
|
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va (VaSet
|
|
)
|
|
xt "108000,48400,110800,49600"
|
|
st "CLK"
|
|
blo "108000,49400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "CLK"
|
|
t "std_ulogic"
|
|
o 17
|
|
)
|
|
)
|
|
)
|
|
*77 (CptPort
|
|
uid 1662,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 1663,0
|
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ro 90
|
|
va (VaSet
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vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "106250,44625,107000,45375"
|
|
)
|
|
tg (CPTG
|
|
uid 1664,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 1665,0
|
|
va (VaSet
|
|
)
|
|
xt "108000,44400,111400,45600"
|
|
st "CS_n"
|
|
blo "108000,45400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "CS_n"
|
|
t "std_ulogic"
|
|
o 15
|
|
)
|
|
)
|
|
)
|
|
*78 (CptPort
|
|
uid 1666,0
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ps "OnEdgeStrategy"
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|
shape (Triangle
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uid 1667,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "106250,46625,107000,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 1668,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1669,0
|
|
va (VaSet
|
|
)
|
|
xt "108000,46400,110700,47600"
|
|
st "SDI"
|
|
blo "108000,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "SDI"
|
|
t "std_ulogic"
|
|
o 16
|
|
)
|
|
)
|
|
)
|
|
*79 (CptPort
|
|
uid 1670,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1671,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "115000,44625,115750,45375"
|
|
)
|
|
tg (CPTG
|
|
uid 1672,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1673,0
|
|
va (VaSet
|
|
)
|
|
xt "111200,44400,114000,45600"
|
|
st "Iout"
|
|
ju 2
|
|
blo "114000,45400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "Iout"
|
|
t "natural"
|
|
o 4
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1650,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "107000,43000,115000,51000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 1651,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*80 (Text
|
|
uid 1652,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,50800,115200,52000"
|
|
st "Curves_test"
|
|
blo "107600,51800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*81 (Text
|
|
uid 1653,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,51800,114100,53000"
|
|
st "DAC_5543"
|
|
blo "107600,52800"
|
|
tm "CptNameMgr"
|
|
)
|
|
*82 (Text
|
|
uid 1654,0
|
|
va (VaSet
|
|
)
|
|
xt "107600,52800,109500,54000"
|
|
st "I4"
|
|
blo "107600,53800"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1655,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1656,0
|
|
text (MLText
|
|
uid 1657,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "72000,28000,72000,28000"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portVis (PortSigDisplay
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*83 (Net
|
|
uid 1674,0
|
|
decl (Decl
|
|
n "CS_X_n"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 16,0
|
|
)
|
|
declText (MLText
|
|
uid 1675,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,18600,16000,19600"
|
|
st "SIGNAL CS_X_n : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*84 (Net
|
|
uid 1682,0
|
|
decl (Decl
|
|
n "CLK_X"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 17,0
|
|
)
|
|
declText (MLText
|
|
uid 1683,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,16600,15800,17600"
|
|
st "SIGNAL CLK_X : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*85 (Net
|
|
uid 1690,0
|
|
decl (Decl
|
|
n "SDI_X"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 18,0
|
|
)
|
|
declText (MLText
|
|
uid 1691,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,22600,15600,23600"
|
|
st "SIGNAL SDI_X : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*86 (Net
|
|
uid 1698,0
|
|
decl (Decl
|
|
n "CS_Y_n"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 19,0
|
|
)
|
|
declText (MLText
|
|
uid 1699,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,19600,16000,20600"
|
|
st "SIGNAL CS_Y_n : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*87 (Net
|
|
uid 1706,0
|
|
decl (Decl
|
|
n "CLK_Y"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 20,0
|
|
)
|
|
declText (MLText
|
|
uid 1707,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,17600,15800,18600"
|
|
st "SIGNAL CLK_Y : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*88 (Net
|
|
uid 1714,0
|
|
decl (Decl
|
|
n "SDI_Y"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 21,0
|
|
)
|
|
declText (MLText
|
|
uid 1715,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,23600,15600,24600"
|
|
st "SIGNAL SDI_Y : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*89 (Net
|
|
uid 1786,0
|
|
decl (Decl
|
|
n "IoutX"
|
|
t "natural"
|
|
o 5
|
|
suid 22,0
|
|
)
|
|
declText (MLText
|
|
uid 1787,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,20600,14100,21600"
|
|
st "SIGNAL IoutX : natural
|
|
"
|
|
)
|
|
)
|
|
*90 (Net
|
|
uid 1788,0
|
|
decl (Decl
|
|
n "IoutY"
|
|
t "natural"
|
|
o 6
|
|
suid 23,0
|
|
)
|
|
declText (MLText
|
|
uid 1789,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,21600,14100,22600"
|
|
st "SIGNAL IoutY : natural
|
|
"
|
|
)
|
|
)
|
|
*91 (Wire
|
|
uid 47,0
|
|
shape (OrthoPolyLine
|
|
uid 48,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "45000,34000,48250,44000"
|
|
pts [
|
|
"45000,44000"
|
|
"45000,34000"
|
|
"48250,34000"
|
|
]
|
|
)
|
|
start &14
|
|
end &47
|
|
sat 2
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 51,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 52,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45000,32600,49100,34000"
|
|
st "reset"
|
|
blo "45000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &1
|
|
)
|
|
*92 (Wire
|
|
uid 55,0
|
|
shape (OrthoPolyLine
|
|
uid 56,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "43000,32000,48250,44000"
|
|
pts [
|
|
"43000,44000"
|
|
"43000,32000"
|
|
"48250,32000"
|
|
]
|
|
)
|
|
start &14
|
|
end &44
|
|
sat 2
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 59,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 60,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45000,30600,48800,32000"
|
|
st "clock"
|
|
blo "45000,31800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*93 (Wire
|
|
uid 760,0
|
|
shape (OrthoPolyLine
|
|
uid 761,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39000,20000,48250,44000"
|
|
pts [
|
|
"48250,20000"
|
|
"39000,20000"
|
|
"39000,44000"
|
|
]
|
|
)
|
|
start &52
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 764,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 765,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "46250,18600,48350,20000"
|
|
st "cs"
|
|
blo "46250,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*94 (Wire
|
|
uid 768,0
|
|
shape (OrthoPolyLine
|
|
uid 769,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "37000,18000,48250,44000"
|
|
pts [
|
|
"48250,18000"
|
|
"37000,18000"
|
|
"37000,44000"
|
|
]
|
|
)
|
|
start &53
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 772,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 773,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45250,16600,48350,18000"
|
|
st "wrL"
|
|
blo "45250,17800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*95 (Wire
|
|
uid 776,0
|
|
shape (OrthoPolyLine
|
|
uid 777,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "35000,16000,48250,44000"
|
|
pts [
|
|
"48250,16000"
|
|
"35000,16000"
|
|
"35000,44000"
|
|
]
|
|
)
|
|
start &51
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 780,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 781,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "44250,14600,47550,16000"
|
|
st "wrH"
|
|
blo "44250,15800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*96 (Wire
|
|
uid 784,0
|
|
shape (OrthoPolyLine
|
|
uid 785,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "33000,14000,48250,44000"
|
|
pts [
|
|
"48250,14000"
|
|
"33000,14000"
|
|
"33000,44000"
|
|
]
|
|
)
|
|
start &50
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 788,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 789,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "46250,12600,48350,14000"
|
|
st "rd"
|
|
blo "46250,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*97 (Wire
|
|
uid 792,0
|
|
shape (OrthoPolyLine
|
|
uid 793,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,8000,79000,44000"
|
|
pts [
|
|
"65750,8000"
|
|
"79000,8000"
|
|
"79000,44000"
|
|
]
|
|
)
|
|
start &48
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 796,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 797,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,6600,71350,8000"
|
|
st "outY"
|
|
blo "67750,7800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*98 (Wire
|
|
uid 800,0
|
|
shape (OrthoPolyLine
|
|
uid 801,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,6000,81000,44000"
|
|
pts [
|
|
"65750,6000"
|
|
"81000,6000"
|
|
"81000,44000"
|
|
]
|
|
)
|
|
start &46
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 804,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 805,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,4600,71450,6000"
|
|
st "outX"
|
|
blo "67750,5800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &23
|
|
)
|
|
*99 (Wire
|
|
uid 808,0
|
|
shape (OrthoPolyLine
|
|
uid 809,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "29000,10000,48250,44000"
|
|
pts [
|
|
"48250,10000"
|
|
"29000,10000"
|
|
"29000,44000"
|
|
]
|
|
)
|
|
start &54
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 812,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 813,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "42250,8600,48250,10000"
|
|
st "dataOut"
|
|
blo "42250,9800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*100 (Wire
|
|
uid 816,0
|
|
shape (OrthoPolyLine
|
|
uid 817,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "27000,8000,48250,44000"
|
|
pts [
|
|
"48250,8000"
|
|
"27000,8000"
|
|
"27000,44000"
|
|
]
|
|
)
|
|
start &49
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 820,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 821,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43250,6600,48250,8000"
|
|
st "dataIn"
|
|
blo "43250,7800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &25
|
|
)
|
|
*101 (Wire
|
|
uid 824,0
|
|
shape (OrthoPolyLine
|
|
uid 825,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "25000,6000,48250,44000"
|
|
pts [
|
|
"48250,6000"
|
|
"25000,6000"
|
|
"25000,44000"
|
|
]
|
|
)
|
|
start &45
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 828,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 829,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "44250,4600,47950,6000"
|
|
st "addr"
|
|
blo "44250,5800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &26
|
|
)
|
|
*102 (Wire
|
|
uid 1009,0
|
|
shape (OrthoPolyLine
|
|
uid 1010,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "99000,11000,106250,11000"
|
|
pts [
|
|
"106250,11000"
|
|
"99000,11000"
|
|
]
|
|
)
|
|
start &35
|
|
sat 32
|
|
eat 16
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1013,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1014,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "101000,9600,108300,11000"
|
|
st "lowpassIn"
|
|
blo "101000,10800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &39
|
|
)
|
|
*103 (Wire
|
|
uid 1015,0
|
|
shape (OrthoPolyLine
|
|
uid 1016,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "103000,15000,106250,15000"
|
|
pts [
|
|
"103000,15000"
|
|
"106250,15000"
|
|
]
|
|
)
|
|
end &32
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1019,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1020,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "102000,13600,105800,15000"
|
|
st "clock"
|
|
blo "102000,14800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*104 (Wire
|
|
uid 1021,0
|
|
shape (OrthoPolyLine
|
|
uid 1022,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "103000,17000,106250,17000"
|
|
pts [
|
|
"103000,17000"
|
|
"106250,17000"
|
|
]
|
|
)
|
|
end &34
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1025,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1026,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "102000,15600,106100,17000"
|
|
st "reset"
|
|
blo "102000,16800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &1
|
|
)
|
|
*105 (Wire
|
|
uid 1027,0
|
|
shape (OrthoPolyLine
|
|
uid 1028,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "123750,11000,131000,11000"
|
|
pts [
|
|
"123750,11000"
|
|
"131000,11000"
|
|
]
|
|
)
|
|
start &33
|
|
sat 32
|
|
eat 16
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1031,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1032,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "126750,9600,135850,11000"
|
|
st "lowpassOut"
|
|
blo "126750,10800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &40
|
|
)
|
|
*106 (Wire
|
|
uid 1191,0
|
|
shape (OrthoPolyLine
|
|
uid 1192,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,30000,73000,44000"
|
|
pts [
|
|
"65750,30000"
|
|
"73000,30000"
|
|
"73000,44000"
|
|
]
|
|
)
|
|
start &56
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1195,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1196,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,28600,74650,30000"
|
|
st "selSinCos"
|
|
blo "67750,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &41
|
|
)
|
|
*107 (Wire
|
|
uid 1479,0
|
|
shape (OrthoPolyLine
|
|
uid 1480,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,10000,77000,44000"
|
|
pts [
|
|
"65750,10000"
|
|
"77000,10000"
|
|
"77000,44000"
|
|
]
|
|
)
|
|
start &57
|
|
end &14
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1483,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1484,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,8600,71450,10000"
|
|
st "outZ"
|
|
blo "67750,9800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &42
|
|
)
|
|
*108 (Wire
|
|
uid 1676,0
|
|
shape (OrthoPolyLine
|
|
uid 1677,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,14000,73000,14000"
|
|
pts [
|
|
"65750,14000"
|
|
"73000,14000"
|
|
]
|
|
)
|
|
start &59
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1680,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1681,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,12600,73450,14000"
|
|
st "CS_X_n"
|
|
blo "67750,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &83
|
|
)
|
|
*109 (Wire
|
|
uid 1684,0
|
|
shape (OrthoPolyLine
|
|
uid 1685,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,16000,73000,16000"
|
|
pts [
|
|
"65750,16000"
|
|
"73000,16000"
|
|
]
|
|
)
|
|
start &58
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1688,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1689,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,14600,72550,16000"
|
|
st "CLK_X"
|
|
blo "67750,15800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &84
|
|
)
|
|
*110 (Wire
|
|
uid 1692,0
|
|
shape (OrthoPolyLine
|
|
uid 1693,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,18000,73000,18000"
|
|
pts [
|
|
"65750,18000"
|
|
"73000,18000"
|
|
]
|
|
)
|
|
start &60
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1696,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1697,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,16600,72350,18000"
|
|
st "SDI_X"
|
|
blo "67750,17800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &85
|
|
)
|
|
*111 (Wire
|
|
uid 1700,0
|
|
shape (OrthoPolyLine
|
|
uid 1701,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,22000,73000,22000"
|
|
pts [
|
|
"65750,22000"
|
|
"73000,22000"
|
|
]
|
|
)
|
|
start &61
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1704,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1705,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,20600,73350,22000"
|
|
st "CS_Y_n"
|
|
blo "67750,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &86
|
|
)
|
|
*112 (Wire
|
|
uid 1708,0
|
|
shape (OrthoPolyLine
|
|
uid 1709,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,24000,73000,24000"
|
|
pts [
|
|
"65750,24000"
|
|
"73000,24000"
|
|
]
|
|
)
|
|
start &63
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1712,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1713,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,22600,72450,24000"
|
|
st "CLK_Y"
|
|
blo "67750,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &87
|
|
)
|
|
*113 (Wire
|
|
uid 1716,0
|
|
shape (OrthoPolyLine
|
|
uid 1717,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65750,26000,73000,26000"
|
|
pts [
|
|
"65750,26000"
|
|
"73000,26000"
|
|
]
|
|
)
|
|
start &62
|
|
sat 32
|
|
eat 16
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1720,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1721,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "67750,24600,72250,26000"
|
|
st "SDI_Y"
|
|
blo "67750,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &88
|
|
)
|
|
*114 (Wire
|
|
uid 1722,0
|
|
shape (OrthoPolyLine
|
|
uid 1723,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,29000,106250,29000"
|
|
pts [
|
|
"99000,29000"
|
|
"106250,29000"
|
|
]
|
|
)
|
|
end &69
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1728,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1729,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,27600,104700,29000"
|
|
st "CS_X_n"
|
|
blo "99000,28800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &83
|
|
)
|
|
*115 (Wire
|
|
uid 1730,0
|
|
shape (OrthoPolyLine
|
|
uid 1731,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,47000,106250,47000"
|
|
pts [
|
|
"99000,47000"
|
|
"106250,47000"
|
|
]
|
|
)
|
|
end &78
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1736,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1737,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,45600,103500,47000"
|
|
st "SDI_Y"
|
|
blo "99000,46800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &88
|
|
)
|
|
*116 (Wire
|
|
uid 1738,0
|
|
shape (OrthoPolyLine
|
|
uid 1739,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,49000,106250,49000"
|
|
pts [
|
|
"99000,49000"
|
|
"106250,49000"
|
|
]
|
|
)
|
|
end &76
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1744,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1745,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,47600,103700,49000"
|
|
st "CLK_Y"
|
|
blo "99000,48800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &87
|
|
)
|
|
*117 (Wire
|
|
uid 1746,0
|
|
shape (OrthoPolyLine
|
|
uid 1747,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,33000,106250,33000"
|
|
pts [
|
|
"99000,33000"
|
|
"106250,33000"
|
|
]
|
|
)
|
|
end &68
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1752,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1753,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,31600,103800,33000"
|
|
st "CLK_X"
|
|
blo "99000,32800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &84
|
|
)
|
|
*118 (Wire
|
|
uid 1754,0
|
|
shape (OrthoPolyLine
|
|
uid 1755,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,31000,106250,31000"
|
|
pts [
|
|
"99000,31000"
|
|
"106250,31000"
|
|
]
|
|
)
|
|
end &70
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1760,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1761,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,29600,103600,31000"
|
|
st "SDI_X"
|
|
blo "99000,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &85
|
|
)
|
|
*119 (Wire
|
|
uid 1762,0
|
|
shape (OrthoPolyLine
|
|
uid 1763,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "99000,45000,106250,45000"
|
|
pts [
|
|
"99000,45000"
|
|
"106250,45000"
|
|
]
|
|
)
|
|
end &77
|
|
es 0
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1768,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1769,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,43600,104600,45000"
|
|
st "CS_Y_n"
|
|
blo "99000,44800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &86
|
|
)
|
|
*120 (Wire
|
|
uid 1772,0
|
|
shape (OrthoPolyLine
|
|
uid 1773,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "115750,29000,123000,29000"
|
|
pts [
|
|
"115750,29000"
|
|
"123000,29000"
|
|
]
|
|
)
|
|
start &71
|
|
sat 32
|
|
eat 16
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1776,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1777,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "117750,27600,121950,29000"
|
|
st "IoutX"
|
|
blo "117750,28800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &89
|
|
)
|
|
*121 (Wire
|
|
uid 1780,0
|
|
shape (OrthoPolyLine
|
|
uid 1781,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "115750,45000,123000,45000"
|
|
pts [
|
|
"115750,45000"
|
|
"123000,45000"
|
|
]
|
|
)
|
|
start &79
|
|
sat 32
|
|
eat 16
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1784,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1785,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "117750,43600,121850,45000"
|
|
st "IoutY"
|
|
blo "117750,44800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &90
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *122 (PackageList
|
|
uid 142,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*123 (Text
|
|
uid 143,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*124 (MLText
|
|
uid 144,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,17500,4600"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 145,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*125 (Text
|
|
uid 146,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*126 (Text
|
|
uid 147,0
|
|
va (VaSet
|
|
isHidden 1
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(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*149 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*150 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*151 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*152 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7600,7000,8600"
|
|
st "Declarations"
|
|
blo "0,8400"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,8600,3400,9600"
|
|
st "Ports:"
|
|
blo "0,9400"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,9600,4800,10600"
|
|
st "Pre User:"
|
|
blo "0,10400"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,10600,22100,15600"
|
|
st "constant addressBitNb: positive := 24;
|
|
constant dataBitNb: positive := 16;
|
|
constant signalBitNb: positive := 16;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,15600,9000,16600"
|
|
st "Diagram Signals:"
|
|
blo "0,16400"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7600,6000,8600"
|
|
st "Post User:"
|
|
blo "0,8400"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,7600,0,7600"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 23,0
|
|
usingSuid 1
|
|
emptyRow *153 (LEmptyRow
|
|
)
|
|
uid 1837,0
|
|
optionalChildren [
|
|
*154 (RefLabelRowHdr
|
|
)
|
|
*155 (TitleRowHdr
|
|
)
|
|
*156 (FilterRowHdr
|
|
)
|
|
*157 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*158 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*159 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*160 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*161 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*162 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*163 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*164 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*165 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*166 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 20
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 1790,0
|
|
)
|
|
*167 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 1792,0
|
|
)
|
|
*168 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "cs"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 1794,0
|
|
)
|
|
*169 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "wrL"
|
|
t "std_ulogic"
|
|
o 23
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 1796,0
|
|
)
|
|
*170 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "wrH"
|
|
t "std_ulogic"
|
|
o 22
|
|
suid 5,0
|
|
)
|
|
)
|
|
uid 1798,0
|
|
)
|
|
*171 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "rd"
|
|
t "std_ulogic"
|
|
o 19
|
|
suid 6,0
|
|
)
|
|
)
|
|
uid 1800,0
|
|
)
|
|
*172 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 17
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 1802,0
|
|
)
|
|
*173 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 16
|
|
suid 8,0
|
|
)
|
|
)
|
|
uid 1804,0
|
|
)
|
|
*174 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_logic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 13
|
|
suid 9,0
|
|
)
|
|
)
|
|
uid 1806,0
|
|
)
|
|
*175 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 12
|
|
suid 10,0
|
|
)
|
|
)
|
|
uid 1808,0
|
|
)
|
|
*176 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "addr"
|
|
t "unsigned"
|
|
b "(addressBitNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 1810,0
|
|
)
|
|
*177 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 14
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 1812,0
|
|
)
|
|
*178 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 15
|
|
suid 13,0
|
|
)
|
|
)
|
|
uid 1814,0
|
|
)
|
|
*179 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 21
|
|
suid 14,0
|
|
)
|
|
)
|
|
uid 1816,0
|
|
)
|
|
*180 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outZ"
|
|
t "std_ulogic"
|
|
o 18
|
|
suid 15,0
|
|
)
|
|
)
|
|
uid 1818,0
|
|
)
|
|
*181 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CS_X_n"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 16,0
|
|
)
|
|
)
|
|
uid 1820,0
|
|
)
|
|
*182 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CLK_X"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 17,0
|
|
)
|
|
)
|
|
uid 1822,0
|
|
)
|
|
*183 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SDI_X"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 1824,0
|
|
)
|
|
*184 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CS_Y_n"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 19,0
|
|
)
|
|
)
|
|
uid 1826,0
|
|
)
|
|
*185 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "CLK_Y"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 1828,0
|
|
)
|
|
*186 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "SDI_Y"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 1830,0
|
|
)
|
|
*187 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "IoutX"
|
|
t "natural"
|
|
o 5
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 1832,0
|
|
)
|
|
*188 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "IoutY"
|
|
t "natural"
|
|
o 6
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 1834,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1850,0
|
|
optionalChildren [
|
|
*189 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
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|
groupVa (MVa
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|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
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|
emptyMRCItem *190 (MRCItem
|
|
litem &153
|
|
pos 23
|
|
dimension 20
|
|
)
|
|
uid 1852,0
|
|
optionalChildren [
|
|
*191 (MRCItem
|
|
litem &154
|
|
pos 0
|
|
dimension 20
|
|
uid 1853,0
|
|
)
|
|
*192 (MRCItem
|
|
litem &155
|
|
pos 1
|
|
dimension 23
|
|
uid 1854,0
|
|
)
|
|
*193 (MRCItem
|
|
litem &156
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1855,0
|
|
)
|
|
*194 (MRCItem
|
|
litem &166
|
|
pos 0
|
|
dimension 20
|
|
uid 1791,0
|
|
)
|
|
*195 (MRCItem
|
|
litem &167
|
|
pos 1
|
|
dimension 20
|
|
uid 1793,0
|
|
)
|
|
*196 (MRCItem
|
|
litem &168
|
|
pos 2
|
|
dimension 20
|
|
uid 1795,0
|
|
)
|
|
*197 (MRCItem
|
|
litem &169
|
|
pos 3
|
|
dimension 20
|
|
uid 1797,0
|
|
)
|
|
*198 (MRCItem
|
|
litem &170
|
|
pos 4
|
|
dimension 20
|
|
uid 1799,0
|
|
)
|
|
*199 (MRCItem
|
|
litem &171
|
|
pos 5
|
|
dimension 20
|
|
uid 1801,0
|
|
)
|
|
*200 (MRCItem
|
|
litem &172
|
|
pos 6
|
|
dimension 20
|
|
uid 1803,0
|
|
)
|
|
*201 (MRCItem
|
|
litem &173
|
|
pos 7
|
|
dimension 20
|
|
uid 1805,0
|
|
)
|
|
*202 (MRCItem
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|
litem &174
|
|
pos 8
|
|
dimension 20
|
|
uid 1807,0
|
|
)
|
|
*203 (MRCItem
|
|
litem &175
|
|
pos 9
|
|
dimension 20
|
|
uid 1809,0
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|
)
|
|
*204 (MRCItem
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|
litem &176
|
|
pos 10
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|
dimension 20
|
|
uid 1811,0
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|
)
|
|
*205 (MRCItem
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|
litem &177
|
|
pos 11
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|
dimension 20
|
|
uid 1813,0
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)
|
|
*206 (MRCItem
|
|
litem &178
|
|
pos 12
|
|
dimension 20
|
|
uid 1815,0
|
|
)
|
|
*207 (MRCItem
|
|
litem &179
|
|
pos 13
|
|
dimension 20
|
|
uid 1817,0
|
|
)
|
|
*208 (MRCItem
|
|
litem &180
|
|
pos 14
|
|
dimension 20
|
|
uid 1819,0
|
|
)
|
|
*209 (MRCItem
|
|
litem &181
|
|
pos 15
|
|
dimension 20
|
|
uid 1821,0
|
|
)
|
|
*210 (MRCItem
|
|
litem &182
|
|
pos 16
|
|
dimension 20
|
|
uid 1823,0
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)
|
|
*211 (MRCItem
|
|
litem &183
|
|
pos 17
|
|
dimension 20
|
|
uid 1825,0
|
|
)
|
|
*212 (MRCItem
|
|
litem &184
|
|
pos 18
|
|
dimension 20
|
|
uid 1827,0
|
|
)
|
|
*213 (MRCItem
|
|
litem &185
|
|
pos 19
|
|
dimension 20
|
|
uid 1829,0
|
|
)
|
|
*214 (MRCItem
|
|
litem &186
|
|
pos 20
|
|
dimension 20
|
|
uid 1831,0
|
|
)
|
|
*215 (MRCItem
|
|
litem &187
|
|
pos 21
|
|
dimension 20
|
|
uid 1833,0
|
|
)
|
|
*216 (MRCItem
|
|
litem &188
|
|
pos 22
|
|
dimension 20
|
|
uid 1835,0
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|
)
|
|
]
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)
|
|
sheetCol (SheetCol
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|
propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 1856,0
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optionalChildren [
|
|
*217 (MRCItem
|
|
litem &157
|
|
pos 0
|
|
dimension 20
|
|
uid 1857,0
|
|
)
|
|
*218 (MRCItem
|
|
litem &159
|
|
pos 1
|
|
dimension 50
|
|
uid 1858,0
|
|
)
|
|
*219 (MRCItem
|
|
litem &160
|
|
pos 2
|
|
dimension 100
|
|
uid 1859,0
|
|
)
|
|
*220 (MRCItem
|
|
litem &161
|
|
pos 3
|
|
dimension 50
|
|
uid 1860,0
|
|
)
|
|
*221 (MRCItem
|
|
litem &162
|
|
pos 4
|
|
dimension 100
|
|
uid 1861,0
|
|
)
|
|
*222 (MRCItem
|
|
litem &163
|
|
pos 5
|
|
dimension 100
|
|
uid 1862,0
|
|
)
|
|
*223 (MRCItem
|
|
litem &164
|
|
pos 6
|
|
dimension 50
|
|
uid 1863,0
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|
)
|
|
*224 (MRCItem
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|
litem &165
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|
pos 7
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dimension 80
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|
uid 1864,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 1851,0
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vaOverrides [
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]
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)
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]
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)
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uid 1836,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *225 (LEmptyRow
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)
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uid 1866,0
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optionalChildren [
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*226 (RefLabelRowHdr
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)
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|
*227 (TitleRowHdr
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|
)
|
|
*228 (FilterRowHdr
|
|
)
|
|
*229 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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|
)
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|
*230 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
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|
)
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|
*231 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
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*232 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
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)
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|
*233 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
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|
)
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*234 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*235 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*236 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
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|
)
|
|
]
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)
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|
pdm (PhysicalDM
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|
uid 1878,0
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optionalChildren [
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*237 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *238 (MRCItem
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|
litem &225
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|
pos 0
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|
dimension 20
|
|
)
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uid 1880,0
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optionalChildren [
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*239 (MRCItem
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|
litem &226
|
|
pos 0
|
|
dimension 20
|
|
uid 1881,0
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)
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*240 (MRCItem
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|
litem &227
|
|
pos 1
|
|
dimension 23
|
|
uid 1882,0
|
|
)
|
|
*241 (MRCItem
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|
litem &228
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|
pos 2
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hidden 1
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|
dimension 20
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|
uid 1883,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 1884,0
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optionalChildren [
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*242 (MRCItem
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|
litem &229
|
|
pos 0
|
|
dimension 20
|
|
uid 1885,0
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)
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|
*243 (MRCItem
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|
litem &231
|
|
pos 1
|
|
dimension 50
|
|
uid 1886,0
|
|
)
|
|
*244 (MRCItem
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|
litem &232
|
|
pos 2
|
|
dimension 100
|
|
uid 1887,0
|
|
)
|
|
*245 (MRCItem
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|
litem &233
|
|
pos 3
|
|
dimension 100
|
|
uid 1888,0
|
|
)
|
|
*246 (MRCItem
|
|
litem &234
|
|
pos 4
|
|
dimension 50
|
|
uid 1889,0
|
|
)
|
|
*247 (MRCItem
|
|
litem &235
|
|
pos 5
|
|
dimension 50
|
|
uid 1890,0
|
|
)
|
|
*248 (MRCItem
|
|
litem &236
|
|
pos 6
|
|
dimension 80
|
|
uid 1891,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
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|
uid 1879,0
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|
vaOverrides [
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|
]
|
|
)
|
|
]
|
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)
|
|
uid 1865,0
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type 1
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)
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|
activeModelName "BlockDiag"
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