2015 lines
25 KiB
Plaintext
2015 lines
25 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 15,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 151,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "ALUControl"
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t "std_ulogic_vector"
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b "(2 DOWNTO 0)"
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o 5
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suid 1,0
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)
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)
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uid 121,0
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)
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*15 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "ALUSrc"
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t "std_uLogic"
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o 6
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suid 2,0
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)
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)
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uid 123,0
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)
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*16 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "funct3"
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t "std_ulogic_vector"
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b "(2 DOWNTO 0)"
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o 1
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suid 5,0
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)
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)
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uid 129,0
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)
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*17 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "funct7"
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t "std_ulogic"
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o 2
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suid 6,0
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)
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)
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uid 131,0
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)
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*18 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "immSrc"
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t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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o 8
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suid 7,0
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)
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)
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uid 133,0
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)
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*19 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "memWrite"
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t "std_ulogic"
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o 9
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suid 8,0
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)
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)
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uid 135,0
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)
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*20 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "op"
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t "std_ulogic_vector"
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b "(6 DOWNTO 0)"
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o 3
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suid 9,0
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)
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)
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uid 137,0
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)
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*21 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "PCSrc"
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t "std_uLogic"
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o 7
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suid 10,0
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)
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)
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uid 139,0
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)
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*22 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "regwrite"
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t "std_ulogic"
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o 10
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suid 11,0
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)
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)
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uid 141,0
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)
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*23 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "resultSrc"
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t "std_ulogic_vector"
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b "(1 downto 0)"
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o 11
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suid 12,0
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)
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)
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uid 143,0
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)
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*24 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "zero"
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t "std_ulogic"
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o 4
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suid 14,0
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)
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)
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uid 147,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 164,0
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optionalChildren [
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*25 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *26 (MRCItem
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litem &1
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pos 11
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dimension 20
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)
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uid 166,0
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optionalChildren [
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*27 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 167,0
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)
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*28 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 168,0
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)
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*29 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 169,0
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)
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*30 (MRCItem
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litem &14
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pos 10
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dimension 20
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uid 122,0
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)
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*31 (MRCItem
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litem &15
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pos 0
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dimension 20
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uid 124,0
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)
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*32 (MRCItem
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litem &16
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pos 8
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dimension 20
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uid 130,0
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)
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*33 (MRCItem
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litem &17
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pos 9
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dimension 20
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uid 132,0
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)
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*34 (MRCItem
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litem &18
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pos 2
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dimension 20
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uid 134,0
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)
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*35 (MRCItem
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litem &19
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pos 3
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dimension 20
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uid 136,0
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)
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*36 (MRCItem
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litem &20
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pos 7
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dimension 20
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uid 138,0
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)
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*37 (MRCItem
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litem &21
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pos 1
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dimension 20
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uid 140,0
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)
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*38 (MRCItem
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litem &22
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pos 4
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dimension 20
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uid 142,0
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)
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*39 (MRCItem
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litem &23
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pos 5
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dimension 20
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uid 144,0
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)
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*40 (MRCItem
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litem &24
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pos 6
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dimension 20
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uid 148,0
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)
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]
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)
|
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sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
|
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uid 170,0
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|
optionalChildren [
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*41 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 171,0
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)
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*42 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 172,0
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)
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*43 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 173,0
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)
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*44 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 174,0
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)
|
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*45 (MRCItem
|
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litem &10
|
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pos 4
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dimension 100
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uid 175,0
|
|
)
|
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*46 (MRCItem
|
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litem &11
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pos 5
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dimension 100
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uid 176,0
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)
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*47 (MRCItem
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litem &12
|
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pos 6
|
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dimension 50
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uid 177,0
|
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)
|
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*48 (MRCItem
|
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litem &13
|
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pos 7
|
|
dimension 80
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|
uid 178,0
|
|
)
|
|
]
|
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)
|
|
fixedCol 4
|
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fixedRow 2
|
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name "Ports"
|
|
uid 165,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 150,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *49 (LEmptyRow
|
|
)
|
|
uid 180,0
|
|
optionalChildren [
|
|
*50 (RefLabelRowHdr
|
|
)
|
|
*51 (TitleRowHdr
|
|
)
|
|
*52 (FilterRowHdr
|
|
)
|
|
*53 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*54 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*55 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*56 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*57 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*58 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*59 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*60 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*61 (LogGeneric
|
|
generic (GiElement
|
|
name "g_tDec"
|
|
type "time"
|
|
value "25 ps"
|
|
)
|
|
uid 586,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 192,0
|
|
optionalChildren [
|
|
*62 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *63 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 194,0
|
|
optionalChildren [
|
|
*64 (MRCItem
|
|
litem &50
|
|
pos 0
|
|
dimension 20
|
|
uid 195,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &51
|
|
pos 1
|
|
dimension 23
|
|
uid 196,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &52
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 197,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &61
|
|
pos 0
|
|
dimension 20
|
|
uid 587,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 198,0
|
|
optionalChildren [
|
|
*68 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 199,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &55
|
|
pos 1
|
|
dimension 50
|
|
uid 200,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &56
|
|
pos 2
|
|
dimension 100
|
|
uid 201,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &57
|
|
pos 3
|
|
dimension 100
|
|
uid 202,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &58
|
|
pos 4
|
|
dimension 50
|
|
uid 203,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &59
|
|
pos 5
|
|
dimension 50
|
|
uid 204,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &60
|
|
pos 6
|
|
dimension 80
|
|
uid 205,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 193,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 179,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "04.11.2022"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "controlUnit"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "04.11.2022"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "11:20:59"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "HEIRV32_SC"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "controlUnit"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "nov."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "novembre"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "11:20:59"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "controlUnit"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2022"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "22"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 149,0
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optionalChildren [
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|
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|
uid 8,0
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|
optionalChildren [
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|
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uid 51,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 52,0
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va (VaSet
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|
vasetType 1
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|
fg "0,65535,0"
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|
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|
|
xt "32000,27625,32750,28375"
|
|
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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xt "25600,27500,31000,28500"
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st "ALUControl"
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|
ju 2
|
|
blo "31000,28300"
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|
tm "CptPortNameMgr"
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font "Courier New,8,0"
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xt "44000,5600,72000,6400"
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thePort (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "ALUControl"
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uid 56,0
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va (VaSet
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vasetType 1
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xt "32000,29625,32750,30375"
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tg (CPTG
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uid 58,0
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blo "31000,30300"
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font "Courier New,8,0"
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xt "44000,6400,62000,7200"
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st "ALUSrc : OUT std_uLogic ;"
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thePort (LogicalPort
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lang 11
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n "ALUSrc"
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uid 71,0
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xt "15250,32625,16000,33375"
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tg (CPTG
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uid 73,0
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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font "Verdana,8,0"
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xt "17000,32500,20000,33500"
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st "funct3"
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blo "17000,33300"
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tm "CptPortNameMgr"
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)
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dt (MLText
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font "Courier New,8,0"
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xt "44000,2400,72000,3200"
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)
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thePort (LogicalPort
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lang 11
|
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decl (Decl
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n "funct3"
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t "std_ulogic_vector"
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b "(2 DOWNTO 0)"
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)
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)
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uid 76,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 77,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "15250,34625,16000,35375"
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tg (CPTG
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uid 78,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 79,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "17000,34500,20000,35500"
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st "funct7"
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blo "17000,35300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 80,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,3200,62000,4000"
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st "funct7 : IN std_ulogic ;"
|
|
)
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thePort (LogicalPort
|
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lang 11
|
|
decl (Decl
|
|
n "funct7"
|
|
t "std_ulogic"
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|
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)
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)
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*80 (CptPort
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uid 81,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 82,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "32000,31625,32750,32375"
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tg (CPTG
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uid 83,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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uid 84,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "27500,31500,31000,32500"
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st "immSrc"
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|
ju 2
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|
blo "31000,32300"
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tm "CptPortNameMgr"
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uid 85,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,8000,72000,8800"
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st "immSrc : OUT std_ulogic_vector (1 DOWNTO 0) ;"
|
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)
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thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "immSrc"
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|
t "std_ulogic_vector"
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|
b "(1 DOWNTO 0)"
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|
o 8
|
|
suid 7,0
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)
|
|
)
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|
)
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*81 (CptPort
|
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uid 86,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 87,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 88,0
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ps "CptPortTextPlaceStrategy"
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uid 89,0
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va (VaSet
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st "memWrite"
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ju 2
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blo "31000,26300"
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tm "CptPortNameMgr"
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dt (MLText
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uid 90,0
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va (VaSet
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font "Courier New,8,0"
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st "memWrite : OUT std_ulogic ;"
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)
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thePort (LogicalPort
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lang 11
|
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m 1
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decl (Decl
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n "memWrite"
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)
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uid 91,0
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ps "OnEdgeStrategy"
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uid 92,0
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ro 90
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va (VaSet
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va (VaSet
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st "op"
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blo "17000,31300"
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tm "CptPortNameMgr"
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va (VaSet
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font "Courier New,8,0"
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st "op : IN std_ulogic_vector (6 DOWNTO 0) ;"
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thePort (LogicalPort
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lang 11
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decl (Decl
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n "op"
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t "std_ulogic_vector"
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uid 96,0
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ps "OnEdgeStrategy"
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ro 270
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va (VaSet
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uid 98,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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font "Verdana,8,0"
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st "PCSrc"
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blo "17000,24300"
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tm "CptPortNameMgr"
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)
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dt (MLText
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va (VaSet
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font "Courier New,8,0"
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xt "44000,7200,62000,8000"
|
|
st "PCSrc : OUT std_uLogic ;"
|
|
)
|
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thePort (LogicalPort
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lang 11
|
|
m 1
|
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decl (Decl
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n "PCSrc"
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t "std_uLogic"
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|
suid 10,0
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|
)
|
|
)
|
|
)
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*84 (CptPort
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|
uid 101,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 102,0
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va (VaSet
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vasetType 1
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)
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)
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tg (CPTG
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|
uid 103,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 104,0
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|
ro 270
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|
va (VaSet
|
|
font "Verdana,8,0"
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)
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xt "25500,33200,26500,37000"
|
|
st "regwrite"
|
|
blo "26300,37000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
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uid 105,0
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va (VaSet
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|
font "Courier New,8,0"
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|
)
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|
xt "44000,9600,62000,10400"
|
|
st "regwrite : OUT std_ulogic ;"
|
|
)
|
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thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "regwrite"
|
|
t "std_ulogic"
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|
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|
suid 11,0
|
|
)
|
|
)
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|
)
|
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*85 (CptPort
|
|
uid 106,0
|
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ps "OnEdgeStrategy"
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uid 107,0
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va (VaSet
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vasetType 1
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tg (CPTG
|
|
uid 108,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
|
uid 109,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
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)
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|
xt "27100,23500,31000,24500"
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|
st "resultSrc"
|
|
ju 2
|
|
blo "31000,24300"
|
|
tm "CptPortNameMgr"
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)
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|
)
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dt (MLText
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uid 110,0
|
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va (VaSet
|
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font "Courier New,8,0"
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xt "44000,10400,71000,11200"
|
|
st "resultSrc : OUT std_ulogic_vector (1 downto 0)"
|
|
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|
lang 11
|
|
m 1
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|
decl (Decl
|
|
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|
|
b "(1 downto 0)"
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|
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|
|
suid 12,0
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)
|
|
)
|
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)
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|
*86 (CptPort
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|
uid 116,0
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ps "OnEdgeStrategy"
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uid 117,0
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ro 270
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va (VaSet
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|
)
|
|
xt "32000,35625,32750,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 118,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 119,0
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va (VaSet
|
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font "Verdana,8,0"
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)
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xt "28800,35500,31000,36500"
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|
st "zero"
|
|
ju 2
|
|
blo "31000,36300"
|
|
tm "CptPortNameMgr"
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|
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|
|
)
|
|
dt (MLText
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|
uid 120,0
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va (VaSet
|
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font "Courier New,8,0"
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)
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|
xt "44000,4800,62000,5600"
|
|
st "zero : IN std_ulogic ;"
|
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|
|
thePort (LogicalPort
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|
lang 11
|
|
decl (Decl
|
|
n "zero"
|
|
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|
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|
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|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,750,5300,2150"
|
|
st "Buffer0"
|
|
blo "0,1950"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "unsigned"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *103 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "42000,0,49400,1200"
|
|
st "Declarations"
|
|
blo "42000,1000"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "42000,1200,45700,2400"
|
|
st "Ports:"
|
|
blo "42000,2200"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "42000,11200,45200,12400"
|
|
st "User:"
|
|
blo "42000,12200"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "42000,0,50200,1200"
|
|
st "Internal User:"
|
|
blo "42000,1000"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,12400,44000,12400"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "42000,0,42000,0"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 587,0
|
|
okToSyncOnLoad 1
|
|
OkToSyncGenericsOnLoad 1
|
|
activeModelName "Symbol:GEN"
|
|
)
|