1482 lines
19 KiB
Plaintext
1482 lines
19 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 4,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 53,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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|
*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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)
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|
*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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|
tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "instruction"
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t "std_ulogic_vector"
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b "(g_dataWidth-1 DOWNTO 0)"
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o 26
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suid 3,0
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)
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)
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uid 178,0
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)
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*15 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "PC"
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t "unsigned"
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b "(g_dataWidth - 1 DOWNTO 0)"
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o 32
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suid 4,0
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)
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)
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uid 180,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 66,0
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optionalChildren [
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*16 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
emptyMRCItem *17 (MRCItem
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litem &1
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pos 2
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dimension 20
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)
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uid 68,0
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optionalChildren [
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*18 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 69,0
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)
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*19 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 70,0
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)
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*20 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 71,0
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)
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*21 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 179,0
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)
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*22 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 181,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 72,0
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optionalChildren [
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*23 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 73,0
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)
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*24 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 74,0
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)
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*25 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 75,0
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)
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*26 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 76,0
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)
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*27 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 77,0
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)
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*28 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 78,0
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)
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*29 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 79,0
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)
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*30 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 80,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 67,0
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vaOverrides [
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]
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)
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]
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)
|
|
uid 52,0
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|
)
|
|
genericsCommonDM (CommonDM
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|
ldm (LogicalDM
|
|
emptyRow *31 (LEmptyRow
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)
|
|
uid 82,0
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|
optionalChildren [
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|
*32 (RefLabelRowHdr
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)
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*33 (TitleRowHdr
|
|
)
|
|
*34 (FilterRowHdr
|
|
)
|
|
*35 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*36 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*37 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*38 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*39 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*40 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*41 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*42 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*43 (LogGeneric
|
|
generic (GiElement
|
|
name "g_dataWidth"
|
|
type "positive"
|
|
value "32"
|
|
)
|
|
uid 205,0
|
|
)
|
|
*44 (LogGeneric
|
|
generic (GiElement
|
|
name "g_memoryNbBits"
|
|
type "positive"
|
|
value "8"
|
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)
|
|
uid 230,0
|
|
)
|
|
*45 (LogGeneric
|
|
generic (GiElement
|
|
name "g_programFile"
|
|
type "string"
|
|
value "\"\""
|
|
)
|
|
uid 255,0
|
|
)
|
|
*46 (LogGeneric
|
|
generic (GiElement
|
|
name "g_tMemRd"
|
|
type "time"
|
|
value "200 ps"
|
|
)
|
|
uid 280,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 94,0
|
|
optionalChildren [
|
|
*47 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *48 (MRCItem
|
|
litem &31
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 96,0
|
|
optionalChildren [
|
|
*49 (MRCItem
|
|
litem &32
|
|
pos 0
|
|
dimension 20
|
|
uid 97,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &33
|
|
pos 1
|
|
dimension 23
|
|
uid 98,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &34
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 99,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &43
|
|
pos 0
|
|
dimension 20
|
|
uid 206,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &44
|
|
pos 1
|
|
dimension 20
|
|
uid 231,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &45
|
|
pos 2
|
|
dimension 20
|
|
uid 256,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &46
|
|
pos 3
|
|
dimension 20
|
|
uid 281,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 100,0
|
|
optionalChildren [
|
|
*56 (MRCItem
|
|
litem &35
|
|
pos 0
|
|
dimension 20
|
|
uid 101,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &37
|
|
pos 1
|
|
dimension 50
|
|
uid 102,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &38
|
|
pos 2
|
|
dimension 100
|
|
uid 103,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &39
|
|
pos 3
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &40
|
|
pos 4
|
|
dimension 50
|
|
uid 105,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &41
|
|
pos 5
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &42
|
|
pos 6
|
|
dimension 80
|
|
uid 107,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 95,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 81,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instr@memory\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instr@memory\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instr@memory"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instrMemory"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "04.11.2022"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "instrMemory"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "04.11.2022"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "11:00:46"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "HEIRV32_SC"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "instrMemory"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "nov."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "novembre"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instr@memory\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\instrMemory\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "11:00:46"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "instrMemory"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2022"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "22"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*63 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*64 (CptPort
|
|
uid 168,0
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blo "1000,2000"
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tm "PanelText"
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)
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)
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)
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parentGraphicsRef (HdmGraphicsRef
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libraryName "HEIRV32_SC"
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entityName "heirv32_sc"
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viewName "struct.bd"
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defaultSymbolBody (SymbolBody
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shape (Rectangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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)
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xt "26800,14800,32200,16000"
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st "<library>"
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blo "26800,15800"
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va (VaSet
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font "Verdana,9,1"
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)
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st "<cell>"
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blo "26800,17000"
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gi *81 (GenericInterface
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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header "Generic Declarations"
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)
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elements [
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]
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)
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portInstanceVisAsIs 1
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portInstanceVis (PortSigDisplay
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sIVOD 1
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)
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portVis (PortSigDisplay
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sIVOD 1
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)
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)
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defaultCptPort (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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)
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st "In0"
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blo "0,1950"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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thePort (LogicalPort
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lang 11
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defaultCptPortBuffer (CptPort
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "0,1950"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "Courier New,8,0"
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thePort (LogicalPort
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lang 11
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m 3
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decl (Decl
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n "Buffer0"
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b "(15 DOWNTO 0)"
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o 0
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)
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DeclarativeBlock *82 (SymDeclBlock
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uid 1,0
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stg "SymDeclLayoutStrategy"
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declLabel (Text
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uid 2,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "42000,0,49400,1200"
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portLabel (Text
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uid 3,0
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va (VaSet
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font "Verdana,9,1"
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xt "42000,1200,45700,2400"
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externalLabel (Text
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va (VaSet
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font "Verdana,9,1"
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xt "42000,4000,45200,5200"
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st "User:"
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blo "42000,5000"
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)
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internalLabel (Text
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uid 6,0
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va (VaSet
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isHidden 1
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font "Verdana,9,1"
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)
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xt "42000,0,50200,1200"
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)
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externalText (MLText
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uid 5,0
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va (VaSet
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font "Courier New,8,0"
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xt "44000,5200,44000,5200"
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tm "SyDeclarativeTextMgr"
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)
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internalText (MLText
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uid 7,0
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va (VaSet
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isHidden 1
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font "Courier New,8,0"
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)
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xt "42000,0,42000,0"
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tm "SyDeclarativeTextMgr"
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)
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)
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lastUid 327,0
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activeModelName "Symbol:GEN"
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)
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