1190 lines
47 KiB
XML
1190 lines
47 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
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<vendor>stnolting</vendor>
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<name>neorv32</name>
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<series>RISC-V</series>
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<version>1.6.4</version>
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<description>The NEORV32 RISC-V Processor</description>
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<!-- CPU core -->
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<cpu>
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<name>NEORV32</name>
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<revision>r2p0</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<fpuDP>false</fpuDP>
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<dspPresent>false</dspPresent>
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<icachePresent>true</icachePresent>
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<dcachePresent>true</dcachePresent>
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<nvicPrioBits>0</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<!-- defaults for all peripherals -->
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0x00000000</resetMask> <!-- default IO devices do not have a dedicated reset -->
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<!-- Peripherals -->
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<peripherals>
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<!-- CFS -->
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<peripheral>
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<name>CFS</name>
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<description>Custom functions subsystem</description>
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<groupName>CFS</groupName>
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<baseAddress>0xFFFFFE00</baseAddress>
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<interrupt><name>CFS_FIRQ</name><value>1</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x80</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register><name>REG0</name><description>Application-defined</description><addressOffset>0x00</addressOffset></register>
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<register><name>REG1</name><description>Application-defined</description><addressOffset>0x04</addressOffset></register>
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<register><name>REG2</name><description>Application-defined</description><addressOffset>0x08</addressOffset></register>
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<register><name>REG3</name><description>Application-defined</description><addressOffset>0x0C</addressOffset></register>
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<register><name>REG4</name><description>Application-defined</description><addressOffset>0x10</addressOffset></register>
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<register><name>REG5</name><description>Application-defined</description><addressOffset>0x14</addressOffset></register>
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<register><name>REG6</name><description>Application-defined</description><addressOffset>0x18</addressOffset></register>
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<register><name>REG7</name><description>Application-defined</description><addressOffset>0x1C</addressOffset></register>
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<register><name>REG8</name><description>Application-defined</description><addressOffset>0x20</addressOffset></register>
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<register><name>REG9</name><description>Application-defined</description><addressOffset>0x24</addressOffset></register>
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<register><name>REG10</name><description>Application-defined</description><addressOffset>0x28</addressOffset></register>
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<register><name>REG11</name><description>Application-defined</description><addressOffset>0x2C</addressOffset></register>
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<register><name>REG12</name><description>Application-defined</description><addressOffset>0x30</addressOffset></register>
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<register><name>REG13</name><description>Application-defined</description><addressOffset>0x34</addressOffset></register>
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<register><name>REG14</name><description>Application-defined</description><addressOffset>0x38</addressOffset></register>
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<register><name>REG15</name><description>Application-defined</description><addressOffset>0x3C</addressOffset></register>
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<register><name>REG16</name><description>Application-defined</description><addressOffset>0x40</addressOffset></register>
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<register><name>REG17</name><description>Application-defined</description><addressOffset>0x44</addressOffset></register>
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<register><name>REG18</name><description>Application-defined</description><addressOffset>0x48</addressOffset></register>
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<register><name>REG19</name><description>Application-defined</description><addressOffset>0x4C</addressOffset></register>
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<register><name>REG20</name><description>Application-defined</description><addressOffset>0x50</addressOffset></register>
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<register><name>REG21</name><description>Application-defined</description><addressOffset>0x54</addressOffset></register>
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<register><name>REG22</name><description>Application-defined</description><addressOffset>0x58</addressOffset></register>
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<register><name>REG23</name><description>Application-defined</description><addressOffset>0x5C</addressOffset></register>
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<register><name>REG24</name><description>Application-defined</description><addressOffset>0x60</addressOffset></register>
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<register><name>REG25</name><description>Application-defined</description><addressOffset>0x64</addressOffset></register>
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<register><name>REG26</name><description>Application-defined</description><addressOffset>0x68</addressOffset></register>
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<register><name>REG27</name><description>Application-defined</description><addressOffset>0x6C</addressOffset></register>
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<register><name>REG28</name><description>Application-defined</description><addressOffset>0x70</addressOffset></register>
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<register><name>REG29</name><description>Application-defined</description><addressOffset>0x74</addressOffset></register>
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<register><name>REG30</name><description>Application-defined</description><addressOffset>0x78</addressOffset></register>
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<register><name>REG31</name><description>Application-defined</description><addressOffset>0x7C</addressOffset></register>
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</registers>
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</peripheral>
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<!-- PWM -->
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<peripheral>
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<name>PWM</name>
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<description>Pulse-width modulation controller</description>
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<groupName>PWM</groupName>
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<baseAddress>0xFFFFFE80</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x40</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>PWM_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>PWM controller enable flag</description>
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</field>
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<field>
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<name>PWM_CTRL_PRSCx</name>
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<bitRange>[3:1]</bitRange>
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<description>Clock prescaler select</description>
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</field>
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</fields>
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</register>
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<register>
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<name>DUTY0</name>
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<description>Duty cycle register 0</description>
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<addressOffset>0x04</addressOffset>
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</register>
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<register>
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<name>DUTY1</name>
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<description>Duty cycle register 1</description>
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<addressOffset>0x08</addressOffset>
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</register>
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<register>
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<name>DUTY2</name>
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<description>Duty cycle register 2</description>
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<addressOffset>0x0C</addressOffset>
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</register>
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<register>
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<name>DUTY3</name>
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<description>Duty cycle register 3</description>
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<addressOffset>0x10</addressOffset>
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</register>
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<register>
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<name>DUTY4</name>
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<description>Duty cycle register 4</description>
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<addressOffset>0x14</addressOffset>
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</register>
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<register>
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<name>DUTY5</name>
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<description>Duty cycle register 5</description>
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<addressOffset>0x18</addressOffset>
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</register>
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<register>
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<name>DUTY6</name>
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<description>Duty cycle register 6</description>
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<addressOffset>0x1C</addressOffset>
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</register>
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<register>
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<name>DUTY7</name>
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<description>Duty cycle register 7</description>
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<addressOffset>0x20</addressOffset>
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</register>
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<register>
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<name>DUTY8</name>
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<description>Duty cycle register 8</description>
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<addressOffset>0x24</addressOffset>
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</register>
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<register>
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<name>DUTY9</name>
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<description>Duty cycle register 9</description>
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<addressOffset>0x28</addressOffset>
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</register>
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<register>
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<name>DUTY10</name>
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<description>Duty cycle register 10</description>
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<addressOffset>0x2C</addressOffset>
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</register>
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<register>
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<name>DUTY11</name>
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<description>Duty cycle register 11</description>
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<addressOffset>0x30</addressOffset>
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</register>
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<register>
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<name>DUTY12</name>
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<description>Duty cycle register 12</description>
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<addressOffset>0x34</addressOffset>
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</register>
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<register>
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<name>DUTY13</name>
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<description>Duty cycle register 13</description>
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<addressOffset>0x38</addressOffset>
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</register>
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<register>
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<name>DUTY14</name>
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<description>Duty cycle register 14</description>
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<addressOffset>0x3C</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- SLINK -->
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<peripheral>
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<name>SLINK</name>
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<description>Stream link interface</description>
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<groupName>SLINK</groupName>
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<baseAddress>0xFFFFFEC0</baseAddress>
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<interrupt><name>SLINK_RX_FIRQ</name><value>10</value></interrupt>
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<interrupt><name>SLINK_TX_FIRQ</name><value>11</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x40</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>SLINK_CTRL_RX_NUMx</name>
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<access>read-only</access>
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<bitRange>[3:0]</bitRange>
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<description>Number of implemented RX links</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_NUMx</name>
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<access>read-only</access>
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<bitRange>[7:4]</bitRange>
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<description>Number of implemented TX links</description>
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</field>
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<field>
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<name>SLINK_CTRL_RX_FIFO_Sx</name>
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<access>read-only</access>
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<bitRange>[11:8]</bitRange>
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<description>log2(RX FIFO size)</description>
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</field>
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<field>
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<name>SLINK_CTRL_TX_FIFO_Sx</name>
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<access>read-only</access>
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<bitRange>[15:12]</bitRange>
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<description>log2(TX FIFO size)</description>
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</field>
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<field>
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<name>SLINK_CTRL_EN</name>
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<access>read-write</access>
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<bitRange>[31:31]</bitRange>
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<description>SLINK enable flag</description>
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</field>
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</fields>
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</register>
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<register>
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<name>IRQ</name>
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<description>Link interrupt configuration register</description>
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<addressOffset>0x08</addressOffset>
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<fields>
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<field>
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<name>SLINK_IRQ_RX_EN</name>
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<bitRange>[7:0]</bitRange>
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<description>RX link interrupt enable</description>
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</field>
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<field>
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<name>SLINK_IRQ_RX_MODE</name>
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<bitRange>[15:8]</bitRange>
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<description>RX link interrupt mode</description>
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</field>
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<field>
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<name>SLINK_IRQ_TX_EN</name>
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<bitRange>[23:16]</bitRange>
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<description>TX link interrupt enable</description>
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</field>
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<field>
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<name>SLINK_IRQ_TX_MODE</name>
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<bitRange>[31:24]</bitRange>
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<description>TX link interrupt mode</description>
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</field>
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</fields>
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</register>
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<register>
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<name>STATUS</name>
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<description>Link status register</description>
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<addressOffset>0x10</addressOffset>
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<fields>
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<field>
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<name>SLINK_STATUS_RX_AVAIL</name>
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<bitRange>[7:0]</bitRange>
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<description>RX link n FIFO is NOT empty (data available)</description>
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</field>
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<field>
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<name>SLINK_STATUS_TX_FREE</name>
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<bitRange>[15:8]</bitRange>
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<description>TX link n FIFO is NOT full (ready to send)</description>
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</field>
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<field>
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<name>SLINK_STATUS_RX_HALF</name>
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<bitRange>[23:16]</bitRange>
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<description>RX link n FIFO fill level is >= half-full</description>
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</field>
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<field>
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<name>SLINK_STATUS_TX_HALF</name>
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<bitRange>[31:24]</bitRange>
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<description>TX link 0 FIFO fill level is > half-full</description>
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</field>
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</fields>
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</register>
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<register>
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<name>DATA0</name>
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<description>Link 0 RTX data register</description>
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<addressOffset>0x20</addressOffset>
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</register>
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<register>
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<name>DATA1</name>
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<description>Link 1 RTX data register</description>
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<addressOffset>0x24</addressOffset>
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</register>
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<register>
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<name>DATA2</name>
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<description>Link 2 RTX data register</description>
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<addressOffset>0x28</addressOffset>
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</register>
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<register>
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<name>DATA3</name>
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<description>Link 3 RTX data register</description>
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<addressOffset>0x2C</addressOffset>
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</register>
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<register>
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<name>DATA4</name>
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<description>Link 4 RTX data register</description>
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<addressOffset>0x30</addressOffset>
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</register>
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<register>
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<name>DATA5</name>
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<description>Link 5 RTX data register</description>
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<addressOffset>0x34</addressOffset>
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</register>
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<register>
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<name>DATA6</name>
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<description>Link 6 RTX data register</description>
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<addressOffset>0x38</addressOffset>
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</register>
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<register>
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<name>DATA7</name>
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<description>Link 7 RTX data register</description>
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<addressOffset>0x3C</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- GPTMR -->
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<peripheral>
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<name>GPTMR</name>
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<description>General purpose timer</description>
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<groupName>GPTMR</groupName>
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<baseAddress>0xFFFFFF60</baseAddress>
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<interrupt><name>GPTMR_FIRQ</name><value>12</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>GPTMR_CTRL_EN</name>
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<bitRange>[0:0]</bitRange>
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<description>Timer enable flag</description>
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</field>
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<field>
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<name>GPTMR_CTRL_PRSC</name>
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<bitRange>[3:1]</bitRange>
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<description>Clock prescaler select</description>
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</field>
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<field>
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<name>GPTMR_CTRL_MODE</name>
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<bitRange>[4:4]</bitRange>
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<description>Timer mode: 0=single-shot mode, 1=continuous mode</description>
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</field>
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</fields>
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</register>
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<register>
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<name>THRES</name>
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<description>Threshold register</description>
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<addressOffset>0x04</addressOffset>
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</register>
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<register>
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<name>COUNT</name>
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<description>Counter register</description>
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<addressOffset>0x08</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- BUSKEEPER -->
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<peripheral>
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<name>BUSKEEPER</name>
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<description>Bus keeper</description>
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<groupName>BUSKEEPER</groupName>
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<baseAddress>0xFFFFFF7C</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x04</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CTRL</name>
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<description>Control register</description>
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<addressOffset>0x00</addressOffset>
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<fields>
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<field>
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<name>BUSKEEPER_ERR_TYPE</name>
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<bitRange>[0:0]</bitRange>
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<access>read-only</access>
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<description>Bus error type: 0=device error, 1=access timeout</description>
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</field>
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<field>
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<name>BUSKEEPER_ERR_FLAG</name>
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<bitRange>[31:31]</bitRange>
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<description>Sticky error flag, clears after read or write access</description>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<!-- XIRQ -->
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<peripheral>
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<name>XIRQ</name>
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<description>External interrupts controller</description>
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<groupName>XIRQ</groupName>
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<baseAddress>0xFFFFFF80</baseAddress>
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<interrupt><name>XIRQ_FIRQ</name><value>8</value></interrupt>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>IER</name>
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<description>IRQ input enable register</description>
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<addressOffset>0x00</addressOffset>
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</register>
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<register>
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<name>IPR</name>
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<description>IRQ pending/ack/clear register</description>
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<addressOffset>0x04</addressOffset>
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</register>
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<register>
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<name>SCR</name>
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<description>IRQ source register</description>
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<addressOffset>0x08</addressOffset>
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</register>
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</registers>
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</peripheral>
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<!-- MTIME -->
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<peripheral>
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<name>MTIME</name>
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<description>Machine timer</description>
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<groupName>MTIME</groupName>
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<baseAddress>0xFFFFFF90</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>TIME_LO</name>
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<description>System time register - low</description>
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<addressOffset>0x00</addressOffset>
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</register>
|
|
<register>
|
|
<name>TIME_HI</name>
|
|
<description>System time register - high</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TIMECMP_LO</name>
|
|
<description>Time compare register - low</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>TIMECMP_HI</name>
|
|
<description>Time compare register - high</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- UART0 -->
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Primary universal asynchronous receiver and transmitter</description>
|
|
<groupName>UART0</groupName>
|
|
<baseAddress>0xFFFFFFA0</baseAddress>
|
|
|
|
<interrupt><name>UART0_RX_FIRQ</name><value>2</value></interrupt>
|
|
<interrupt><name>UART0_TX_FIRQ</name><value>3</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CTRL_BAUD</name>
|
|
<bitRange>[11:0]</bitRange>
|
|
<description>Baud rate divisor</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_SIM_MODE</name>
|
|
<bitRange>[12:12]</bitRange>
|
|
<description>Simulation output override enable, for use in simulation only</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_EMPTY</name>
|
|
<bitRange>[13:13]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_HALF</name>
|
|
<bitRange>[14:14]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO is at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_FULL</name>
|
|
<bitRange>[15:15]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_EMPTY</name>
|
|
<bitRange>[16:16]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_HALF</name>
|
|
<bitRange>[17:17]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_FULL</name>
|
|
<bitRange>[18:18]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RTS_EN</name>
|
|
<bitRange>[20:20]</bitRange>
|
|
<description>Enable hardware flow control: Assert RTS output if UART.RX is ready to receive</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_CTS_EN</name>
|
|
<bitRange>[21:21]</bitRange>
|
|
<description>Enable hardware flow control: UART.TX starts sending only if CTS input is asserted</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_PMODE0</name>
|
|
<bitRange>[22:22]</bitRange>
|
|
<description>Parity configuration (0=even; 1=odd)</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_PMODE1</name>
|
|
<bitRange>[23:23]</bitRange>
|
|
<description>Parity bit enabled when set</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_PRSC</name>
|
|
<bitRange>[26:24]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_CTS</name>
|
|
<bitRange>[27:27]</bitRange>
|
|
<access>read-only</access>
|
|
<description>current state of CTS input</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_EN</name>
|
|
<bitRange>[28:28]</bitRange>
|
|
<description>UART enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_RX_IRQ</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<description>RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_IRQ</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<description>TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTRL_TX_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Transmitter is busy when set</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>RX/TX data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<description>Receive/transmit data</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_DATA_PERR</name>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX parity error detected when set</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_DATA_FERR</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX frame error (no valid stop bit) detected when set</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_DATA_OVERR</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX parity error detected when set</description>
|
|
</field>
|
|
<field>
|
|
<name>UART_DATA_AVAIL</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>RX data available when set</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- UART1 -->
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<description>Secondary universal asynchronous receiver and transmitter</description>
|
|
<groupName>UART1</groupName>
|
|
<baseAddress>0xFFFFFFD0</baseAddress>
|
|
|
|
<interrupt><name>UART1_RX_FIRQ</name><value>4</value></interrupt>
|
|
<interrupt><name>UART1_TX_FIRQ</name><value>5</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
</peripheral>
|
|
|
|
<!-- SPI -->
|
|
<peripheral>
|
|
<name>SPI</name>
|
|
<description>Serial peripheral interface controller</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0xFFFFFFA8</baseAddress>
|
|
|
|
<interrupt><name>SPI_FIRQ</name><value>6</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_CTRL_CS</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<description>Direct chip select line</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_EN</name>
|
|
<bitRange>[8:8]</bitRange>
|
|
<description>SPI enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CPHA</name>
|
|
<bitRange>[9:9]</bitRange>
|
|
<description>Clock phase</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_PRSC</name>
|
|
<bitRange>[12:10]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_SIZE</name>
|
|
<bitRange>[14:13]</bitRange>
|
|
<description>Data transfer size</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_CPOL</name>
|
|
<bitRange>[15:15]</bitRange>
|
|
<description>Clock polarity</description>
|
|
</field>
|
|
<field>
|
|
<name>SPI_CTRL_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>SPI busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>RX/TX data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- TWI -->
|
|
<peripheral>
|
|
<name>TWI</name>
|
|
<description>Two-wire interface controller</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0xFFFFFFB0</baseAddress>
|
|
|
|
<interrupt><name>TWI_FIRQ</name><value>7</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TWI_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>TWI enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_START</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>Generate START condition, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_STOP</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Generate STOP condition, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_PRSC</name>
|
|
<bitRange>[5:3]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_MACK</name>
|
|
<bitRange>[6:6]</bitRange>
|
|
<description>Generate ACK by controller for each transmission</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_ACK</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>ACK received when set</description>
|
|
</field>
|
|
<field>
|
|
<name>TWI_CTRL_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Transfer in progress, busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>RX/TX data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TWI_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<description>RX/TX data</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- TRNG -->
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<description>True random number generator</description>
|
|
<groupName>TRNG</groupName>
|
|
<baseAddress>0xFFFFFFB8</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control and data register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TRNG_CTRL_DATA</name>
|
|
<bitRange>[7:0]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Random data</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_EN</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<description>TRNG enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_CTRL_VALID</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Random data output valid</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- WDT -->
|
|
<peripheral>
|
|
<name>WDT</name>
|
|
<description>Watchdog timer</description>
|
|
<groupName>WDT</groupName>
|
|
<baseAddress>0xFFFFFFBC</baseAddress>
|
|
|
|
<interrupt><name>WDT_FIRQ</name><value>0</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>WDT_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>WDT enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_CLK_SEL</name>
|
|
<bitRange>[3:1]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_MODE</name>
|
|
<bitRange>[4:4]</bitRange>
|
|
<description>Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_RCAUSE</name>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Cause of last system reset: 0=external reset, 1=watchdog</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_RESET</name>
|
|
<bitRange>[6:6]</bitRange>
|
|
<description>Reset WDT counter when set, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_FORCE</name>
|
|
<bitRange>[7:7]</bitRange>
|
|
<description>Force WDT action, auto-clears</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_LOCK</name>
|
|
<bitRange>[8:8]</bitRange>
|
|
<description>Lock write access to control register, clears on reset (HW or WDT) only</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_DBEN</name>
|
|
<bitRange>[9:9]</bitRange>
|
|
<description>Allow WDT to continue operation even when in debug mode</description>
|
|
</field>
|
|
<field>
|
|
<name>WDT_CTRL_HALF</name>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>read-only</access>
|
|
<description>Set if at least half of the max. timeout counter value has been reached</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- GPIO -->
|
|
<peripheral>
|
|
<name>GPIO</name>
|
|
<description>General purpose input/output port</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0xFFFFFFc0</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>INPUT_LO</name>
|
|
<description>Parallel input register - low</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>INPUT_HI</name>
|
|
<description>Parallel input register - high</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT_LO</name>
|
|
<description>Parallel output register - low</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT_HI</name>
|
|
<description>Parallel output register - high</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- NEOLED -->
|
|
<peripheral>
|
|
<name>NEOLED</name>
|
|
<description>Smart LED hardware interface</description>
|
|
<groupName>NEOLED</groupName>
|
|
<baseAddress>0xFFFFFFD8</baseAddress>
|
|
|
|
<interrupt><name>NEOLED_FIRQ</name><value>9</value></interrupt>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x08</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NEOLED_CTRL_EN</name>
|
|
<bitRange>[0:0]</bitRange>
|
|
<description>NEOLED enable flag</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_MODE</name>
|
|
<bitRange>[1:1]</bitRange>
|
|
<description>TX mode (0=24-bit, 1=32-bit)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_STROBE</name>
|
|
<bitRange>[2:2]</bitRange>
|
|
<description>Strobe (0=send normal data, 1=send RESET command on data write)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_PRSC</name>
|
|
<bitRange>[5:3]</bitRange>
|
|
<description>Clock prescaler select</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_BUFS</name>
|
|
<bitRange>[9:6]</bitRange>
|
|
<access>read-only</access>
|
|
<description>log2(tx buffer size)</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_TOT</name>
|
|
<bitRange>[14:10]</bitRange>
|
|
<description>pulse-clock ticks per total period bit</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_ZERO_H</name>
|
|
<bitRange>[19:15]</bitRange>
|
|
<description>pulse-clock ticks per ZERO high-time</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_T_ONE_H</name>
|
|
<bitRange>[24:20]</bitRange>
|
|
<description>pulse-clock ticks per ONE high-time</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_IRQ_CONF</name>
|
|
<bitRange>[27:27]</bitRange>
|
|
<description>TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_EMPTY</name>
|
|
<bitRange>[28:28]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is empty</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_HALF</name>
|
|
<bitRange>[29:29]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is at least half-full</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_FULL</name>
|
|
<bitRange>[30:30]</bitRange>
|
|
<access>read-only</access>
|
|
<description>TX FIFO is full</description>
|
|
</field>
|
|
<field>
|
|
<name>NEOLED_CTRL_TX_BUSY</name>
|
|
<bitRange>[31:31]</bitRange>
|
|
<access>read-only</access>
|
|
<description>busy flag</description>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<!-- SYSINFO -->
|
|
<peripheral>
|
|
<name>SYSINFO</name>
|
|
<description>System configuration information memory</description>
|
|
<groupName>SYSINFO</groupName>
|
|
<baseAddress>0xFFFFFFE0</baseAddress>
|
|
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CLK</name>
|
|
<description>Clock speed in Hz</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>CPU</name>
|
|
<description>CPU core features</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_CPU_ZICSR</name><bitRange>[0:0]</bitRange><description>Zicsr extension (I sub-extension) available when set</description></field>
|
|
<field><name>SYSINFO_CPU_ZIFENCEI</name><bitRange>[1:1]</bitRange><description>Zifencei extension (I sub-extension) available when set</description></field>
|
|
<field><name>SYSINFO_CPU_ZMMUL</name><bitRange>[2:2]</bitRange><description>Zmmul extension (M sub-extension) available when set</description></field>
|
|
<field><name>SYSINFO_CPU_ZFINX</name><bitRange>[5:5]</bitRange><description>Zfinx extension (F sub-/alternative-extension) available when set</description></field>
|
|
<field><name>SYSINFO_CPU_ZXSCNT</name><bitRange>[6:6]</bitRange><description>Custom extension - Small CPU counters</description></field>
|
|
<field><name>SYSINFO_CPU_ZICNTR</name><bitRange>[7:7]</bitRange><description>Basic CPU counters available when set</description></field>
|
|
<field><name>SYSINFO_CPU_PMP</name><bitRange>[8:8]</bitRange><description>PMP (physical memory protection) extension available when set</description></field>
|
|
<field><name>SYSINFO_CPU_ZIHPM</name><bitRange>[9:9]</bitRange><description>HPM (hardware performance monitors) extension available when set</description></field>
|
|
<field><name>SYSINFO_CPU_DEBUGMODE</name><bitRange>[10:10]</bitRange><description>RISC-V CPU debug mode available when set</description></field>
|
|
<field><name>SYSINFO_CPU_FASTMUL</name><bitRange>[30:30]</bitRange><description>fast multiplications (via FAST_MUL_EN generic) available when set</description></field>
|
|
<field><name>SYSINFO_CPU_FASTSHIFT</name><bitRange>[31:31]</bitRange><description>fast shifts (via FAST_SHIFT_EN generic) available when set</description></field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOC</name>
|
|
<description>SoC features</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_SOC_BOOTLOADER</name><bitRange>[0:0]</bitRange><description>Bootloader implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_EXT</name><bitRange>[1:1]</bitRange><description>External bus interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_INT_IMEM</name><bitRange>[2:2]</bitRange><description>Processor-internal instruction memory implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_INT_DMEM</name><bitRange>[3:3]</bitRange><description>Processor-internal data memory implemented</description></field>
|
|
<field><name>SYSINFO_SOC_MEM_EXT_ENDIAN</name><bitRange>[4:4]</bitRange><description>External bus interface uses BIG-endian byte-order</description></field>
|
|
<field><name>SYSINFO_SOC_ICACHE</name><bitRange>[5:5]</bitRange><description>Processor-internal instruction cache implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IS_SIM</name><bitRange>[13:13]</bitRange><description>Set if processor is being simulated</description></field>
|
|
<field><name>SYSINFO_SOC_OCD</name><bitRange>[14:14]</bitRange><description>On-chip debugger implemented</description></field>
|
|
<field><name>SYSINFO_SOC_HW_RESET</name><bitRange>[15:15]</bitRange><description>Dedicated hardware reset of core registers implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_GPIO</name><bitRange>[16:16]</bitRange><description>General purpose input/output port unit implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_MTIME</name><bitRange>[17:17]</bitRange><description>Machine system timer implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_UART0</name><bitRange>[18:18]</bitRange><description>Primary universal asynchronous receiver/transmitter 0 implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_SPI</name><bitRange>[19:19]</bitRange><description>Serial peripheral interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_TWI</name><bitRange>[20:20]</bitRange><description>Two-wire interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_PWM</name><bitRange>[21:21]</bitRange><description>Pulse-width modulation unit implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_WDT</name><bitRange>[22:22]</bitRange><description>Watchdog timer implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_CFS</name><bitRange>[23:23]</bitRange><description>Custom functions subsystem implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_TRNG</name><bitRange>[24:24]</bitRange><description>True random number generator implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_SLINK</name><bitRange>[25:25]</bitRange><description>Stream link interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_UART1</name><bitRange>[26:26]</bitRange><description>Secondary universal asynchronous receiver/transmitter 1 implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_NEOLED</name><bitRange>[27:27]</bitRange><description>NeoPixel-compatible smart LED interface implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_XIRQ</name><bitRange>[28:28]</bitRange><description>External interrupt controller implemented</description></field>
|
|
<field><name>SYSINFO_SOC_IO_GPTMR</name><bitRange>[29:29]</bitRange><description>General purpose timer implemented</description></field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CACHE</name>
|
|
<description>Cache configuration</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<access>read-only</access>
|
|
<fields>
|
|
<field><name>SYSINFO_CACHE_IC_BLOCK_SIZE</name><bitRange>[3:0]</bitRange><description>i-cache: log2(Block size in bytes)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_NUM_BLOCKS</name><bitRange>[7:4]</bitRange><description>i-cache: log2(Number of cache blocks/pages/lines)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_ASSOCIATIVITY</name><bitRange>[11:8]</bitRange><description>i-cache: log2(associativity)</description></field>
|
|
<field><name>SYSINFO_CACHE_IC_REPLACEMENT</name><bitRange>[15:12]</bitRange><description>i-cache: replacement policy (0001 = LRU if associativity > 0)</description></field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPACE_BASE</name>
|
|
<description>Instruction memory address space base address</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>DSPACE_BASE</name>
|
|
<description>Data memory address space base address</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>IMEM_SIZE</name>
|
|
<description>Internal instruction memory (IMEM) size in bytes</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
<register>
|
|
<name>DMEM_SIZE</name>
|
|
<description>Internal data memory (DMEM) size in bytes</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<access>read-only</access>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
</peripherals>
|
|
</device>
|