141 lines
4.3 KiB
VHDL
141 lines
4.3 KiB
VHDL
ARCHITECTURE RTL OF flashController IS
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signal addressReg: unsigned(flashAddr'range);
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signal dataOutReg: std_ulogic_vector(flashDataOut'range);
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signal dataInReg: std_ulogic_vector(flashDataIn'range);
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type sequenceStateType is (
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idle,
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waitForBus1, waitForBus0,
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startAccess, waitAcccessEnd
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);
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signal sequenceState: sequenceStateType;
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signal read: std_ulogic;
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signal startCounter: std_ulogic;
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signal sequenceCounter: unsigned(3 downto 0);
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signal endOfCount: std_ulogic;
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signal readDataValid: std_ulogic;
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signal flashCE: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- memory reset
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memRst_n <= not '0';
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------------------------------------------------------------------------------
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-- address
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storeAddress: process(reset, clock)
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begin
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if reset = '1' then
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addressReg <= (others => '0');
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elsif rising_edge(clock) then
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if (flashRd = '1') or (flashWr = '1') then
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addressReg <= shift_left(flashAddr, 1);
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end if;
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end if;
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end process storeAddress;
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memAddress <= std_ulogic_vector(addressReg);
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------------------------------------------------------------------------------
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-- data out
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storeDataOut: process(reset, clock)
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begin
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if reset = '1' then
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dataOutReg <= (others => '0');
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elsif rising_edge(clock) then
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if flashWr = '1' then
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dataOutReg <= flashDataOut;
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end if;
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end if;
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end process storeDataOut;
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memDataOut <= flashDataOut;
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------------------------------------------------------------------------------
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-- data in
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readDataValid <= '1' when (read = '1') and (endOfCount = '1') else '0';
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storeDataIn: process(reset, clock)
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begin
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if reset = '1' then
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dataInReg <= (others => '0');
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elsif rising_edge(clock) then
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if readDataValid = '1' then
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dataInReg <= memDataIn;
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end if;
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end if;
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end process storeDataIn;
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flashDataIn <= dataInReg when readDataValid = '0' else memDataIn;
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------------------------------------------------------------------------------
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-- read/write sequence
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busAccessFsm: process(reset, clock)
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begin
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if reset = '1' then
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read <= '0';
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sequenceState <= idle;
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elsif rising_edge(clock) then
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case sequenceState is
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when idle =>
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if flashRd = '1' then
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read <= '1';
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sequenceState <= waitForBus1;
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elsif flashWr = '1' then
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read <= '0';
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sequenceState <= waitForBus1;
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end if;
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when waitForBus1 =>
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if memBusEn_n = '1' then
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sequenceState <= waitForBus0;
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end if;
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when waitForBus0 =>
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if memBusEn_n = '0' then
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sequenceState <= startAccess;
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end if;
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when startAccess =>
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sequenceState <= waitAcccessEnd;
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when waitAcccessEnd =>
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if endOfCount = '1' then
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sequenceState <= idle;
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end if;
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end case;
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end if;
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end process busAccessFsm;
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startCounter <= '1' when sequenceState = startAccess else '0';
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endOfCount <= '1'
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when ( (sequenceCounter = rdWaitState) and (read = '1') ) or
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( (sequenceCounter = wrWaitState) and (read = '0') )
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else '0';
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countSequence: process(reset, clock)
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begin
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if reset = '1' then
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sequenceCounter <= (others => '0');
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elsif rising_edge(clock) then
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if sequenceCounter = 0 then
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if startCounter = '1' then
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sequenceCounter <= sequenceCounter + 1;
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end if;
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else
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if endOfCount = '1' then
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sequenceCounter <= (others => '0');
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else
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sequenceCounter <= sequenceCounter + 1;
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end if;
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end if;
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end if;
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end process countSequence;
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flashCE <= '0' when sequenceCounter = 0 else '1';
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flashCE_n <= not flashCE;
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memWR_n <= not '1' when (read = '0') and (flashCE = '1') and (endOfCount = '0')
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else not '0';
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memOE_n <= not '1' when (read = '1') and (flashCE = '1') else not '0';
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flashDataValid <= endOfCount;
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END ARCHITECTURE RTL;
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