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SEm-Labos/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd

55 lines
1.6 KiB
VHDL

ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb DOWNTO 0);
type order0 is array (0 to 0) of sample_type;
type order1 is array (0 to 1) of sample_type;
type order2 is array (0 to 2) of sample_type;
type order3 is array (0 to 3) of sample_type;
signal cA: order3;
signal cB: order2;
signal cC: order1;
signal cD: order0;
BEGIN
process(clock, reset) begin
if reset = '1' then
cA <= (others => (others => '0'));
cB <= (others => (others => '0'));
cC <= (others => (others => '0'));
cD <= (others => (others => '0'));
elsif rising_edge(clock) then
if restartPolynom = '1' then
cA(3) <= (others => '0');
cA(2) <= (others => '0');
cA(1) <= (others => '0');
cA(0) <= resize(a,sample_type'high+1);
cB(2) <= (others => '0');
cB(1) <= (others => '0');
cB(0) <= resize(b,sample_type'high+1);
cC(1) <= (others => '0');
cC(0) <= resize(c,sample_type'high+1);
cD(0) <= resize(d,sample_type'high+1);
else
cC(1) <= resize(c,sample_type'high+1) + cC(1);
cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + b;
cB(1) <= resize(b,sample_type'high+1) + cB(1);
cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + a;
cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + a;
cA(1) <= resize(A,sample_type'high+1) + cA(1);
end if;
end if;
end process;
sampleOut <= resize(cA(3)+cB(2)+cC(1)+cD(0),signalBitNb);
END ARCHITECTURE studentVersion;