3651 lines
44 KiB
Plaintext
3651 lines
44 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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(Instance
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name "I_dff"
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duLibraryName "Board"
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duName "DFF"
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elements [
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]
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mwi 0
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uid 1071,0
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)
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(Instance
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name "I_inv2"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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|
uid 1806,0
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)
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|
(Instance
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name "I_inv1"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 1817,0
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)
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(Instance
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name "I_cnt"
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duLibraryName "PipelinedOperators"
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duName "pipelineCounter"
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elements [
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(GiElement
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name "bitNb"
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type "positive"
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value "counterBitNb"
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)
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(GiElement
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name "stageNb"
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type "positive"
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value "pipelineStageNb"
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)
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]
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mwi 0
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uid 2439,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb4"
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number "4"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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|
variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_circuit\\struct.bd.info"
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)
|
|
(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_circuit\\struct.bd.user"
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)
|
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(vvPair
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variable "SourceDir"
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|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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|
variable "appl"
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|
value "HDL Designer"
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)
|
|
(vvPair
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|
variable "arch_name"
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|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
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|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
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|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_circuit"
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|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipelineCounter_circuit"
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)
|
|
(vvPair
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|
variable "date"
|
|
value "28.04.2023"
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|
)
|
|
(vvPair
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|
variable "day"
|
|
value "ven."
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)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
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|
)
|
|
(vvPair
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variable "dd"
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value "28"
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)
|
|
(vvPair
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|
variable "designName"
|
|
value "$DESIGN_NAME"
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)
|
|
(vvPair
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variable "entity_name"
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value "pipelineCounter_circuit"
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)
|
|
(vvPair
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|
variable "ext"
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|
value "<TBD>"
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)
|
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(vvPair
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variable "f"
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|
value "struct.bd"
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)
|
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(vvPair
|
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variable "f_logical"
|
|
value "struct.bd"
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)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
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value "axel.amand"
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)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
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)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
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value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
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value "WE7860"
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)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:18:24"
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|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
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)
|
|
(vvPair
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|
variable "language"
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value "VHDL"
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)
|
|
(vvPair
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|
variable "library"
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value "Board"
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)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
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value "$HDS_PROJECT_DIR/../Board/concat"
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|
)
|
|
(vvPair
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|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
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|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
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|
value "$SCRATCH_DIR/Board"
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)
|
|
(vvPair
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|
variable "library_downstream_QuestaSimCompiler"
|
|
value "$HDS_PROJECT_DIR/../Board/work"
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|
)
|
|
(vvPair
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|
variable "library_downstream_SpyGlass"
|
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value "U:\\SEm_curves\\Synthesis"
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)
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|
(vvPair
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|
variable "library_downstream_SvAssistantInvoke"
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value "$HDS_PROJECT_DIR/../Board/svassistant"
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)
|
|
(vvPair
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variable "mm"
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value "04"
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)
|
|
(vvPair
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|
variable "module_name"
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|
value "pipelineCounter_circuit"
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|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_circuit\\struct.bd"
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|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipelineCounter_circuit\\struct.bd"
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|
)
|
|
(vvPair
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|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:18:24"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "pipelineCounter_circuit"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
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|
)
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LanguageMgr "Vhdl2008LangMgr"
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uid 83,0
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optionalChildren [
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tg (WTG
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uid 13,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 14,0
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va (VaSet
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font "Verdana,12,0"
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st "clock"
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ju 2
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blo "14000,30500"
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tm "WireNameMgr"
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)
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)
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)
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*2 (Net
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uid 21,0
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 1,0
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declText (MLText
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va (VaSet
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shape (CompositeShape
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va (VaSet
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optionalChildren [
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pts [
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tg (WTG
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uid 41,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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blo "14000,42500"
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tm "WireNameMgr"
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uid 49,0
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decl (Decl
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n "reset"
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t "std_ulogic"
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suid 2,0
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declText (MLText
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va (VaSet
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uid 1058,0
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va (VaSet
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stg "VerticalLayoutStrategy"
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thePort (LogicalPort
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va (VaSet
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tg (CPTG
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uid 1069,0
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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va (VaSet
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ttg (MlTextGroup
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uid 1077,0
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ps "EdgeToEdgeStrategy"
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text (MLText
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va (VaSet
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uid 1806,0
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uid 1797,0
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va (VaSet
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va (VaSet
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tg (CPTG
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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uid 1815,0
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blo "45000,34900"
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thePort (LogicalPort
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decl (Decl
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n "in1"
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suid 1,0
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uid 1802,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1803,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 1804,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 1805,0
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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xt "46050,33500,49750,34900"
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st "out1"
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ju 2
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blo "49750,34700"
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uid 1816,0
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va (VaSet
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ju 2
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thePort (LogicalPort
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m 1
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n "out1"
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suid 2,0
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|
|
)
|
|
]
|
|
shape (Buf
|
|
uid 1807,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "45000,31000,50000,37000"
|
|
)
|
|
showPorts 0
|
|
oxt "23000,4000,28000,10000"
|
|
ttg (MlTextGroup
|
|
uid 1808,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*37 (Text
|
|
uid 1809,0
|
|
va (VaSet
|
|
)
|
|
xt "46460,36700,50060,37900"
|
|
st "Board"
|
|
blo "46460,37700"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*38 (Text
|
|
uid 1810,0
|
|
va (VaSet
|
|
)
|
|
xt "46460,37700,52860,38900"
|
|
st "inverterIn"
|
|
blo "46460,38700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*39 (Text
|
|
uid 1811,0
|
|
va (VaSet
|
|
)
|
|
xt "46460,38700,50460,39900"
|
|
st "I_inv2"
|
|
blo "46460,39700"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1812,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1813,0
|
|
text (MLText
|
|
uid 1814,0
|
|
va (VaSet
|
|
)
|
|
xt "45000,37400,45000,37400"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portVis (PortSigDisplay
|
|
disp 1
|
|
sN 0
|
|
sTC 0
|
|
sT 1
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*40 (SaComponent
|
|
uid 1817,0
|
|
optionalChildren [
|
|
*41 (CptPort
|
|
uid 1826,0
|
|
optionalChildren [
|
|
*42 (Circle
|
|
uid 1831,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "22092,41546,23000,42454"
|
|
radius 454
|
|
)
|
|
]
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1827,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "21342,41625,22092,42375"
|
|
)
|
|
tg (CPTG
|
|
uid 1828,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1829,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "23000,41500,25700,42900"
|
|
st "in1"
|
|
blo "23000,42700"
|
|
)
|
|
s (Text
|
|
uid 1830,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "23000,42900,23000,42900"
|
|
blo "23000,42900"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "in1"
|
|
t "std_uLogic"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*43 (CptPort
|
|
uid 1832,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1833,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "28000,41625,28750,42375"
|
|
)
|
|
tg (CPTG
|
|
uid 1834,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1835,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "24050,41500,27750,42900"
|
|
st "out1"
|
|
ju 2
|
|
blo "27750,42700"
|
|
)
|
|
s (Text
|
|
uid 1836,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "27750,42900,27750,42900"
|
|
ju 2
|
|
blo "27750,42900"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "out1"
|
|
t "std_uLogic"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Buf
|
|
uid 1818,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "23000,39000,28000,45000"
|
|
)
|
|
showPorts 0
|
|
oxt "23000,4000,28000,10000"
|
|
ttg (MlTextGroup
|
|
uid 1819,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*44 (Text
|
|
uid 1820,0
|
|
va (VaSet
|
|
)
|
|
xt "24460,44700,28060,45900"
|
|
st "Board"
|
|
blo "24460,45700"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*45 (Text
|
|
uid 1821,0
|
|
va (VaSet
|
|
)
|
|
xt "24460,45700,30860,46900"
|
|
st "inverterIn"
|
|
blo "24460,46700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*46 (Text
|
|
uid 1822,0
|
|
va (VaSet
|
|
)
|
|
xt "24460,46700,28460,47900"
|
|
st "I_inv1"
|
|
blo "24460,47700"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1823,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1824,0
|
|
text (MLText
|
|
uid 1825,0
|
|
va (VaSet
|
|
)
|
|
xt "23000,45400,23000,45400"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portVis (PortSigDisplay
|
|
disp 1
|
|
sN 0
|
|
sTC 0
|
|
sT 1
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*47 (SaComponent
|
|
uid 2439,0
|
|
optionalChildren [
|
|
*48 (CptPort
|
|
uid 2427,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2428,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "73000,29625,73750,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 2429,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2430,0
|
|
va (VaSet
|
|
)
|
|
xt "66600,29550,72000,30750"
|
|
st "countOut"
|
|
ju 2
|
|
blo "72000,30550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(bitNb-1 downto 0)"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*49 (CptPort
|
|
uid 2431,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2432,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "56250,29625,57000,30375"
|
|
)
|
|
tg (CPTG
|
|
uid 2433,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2434,0
|
|
va (VaSet
|
|
)
|
|
xt "58000,29400,61400,30600"
|
|
st "clock"
|
|
blo "58000,30400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*50 (CptPort
|
|
uid 2435,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2436,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "56250,31625,57000,32375"
|
|
)
|
|
tg (CPTG
|
|
uid 2437,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2438,0
|
|
va (VaSet
|
|
)
|
|
xt "58000,31550,61300,32750"
|
|
st "reset"
|
|
blo "58000,32550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 2440,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "57000,26000,73000,34000"
|
|
)
|
|
oxt "32000,15000,48000,23000"
|
|
ttg (MlTextGroup
|
|
uid 2441,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*51 (Text
|
|
uid 2442,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "57600,33800,68400,35000"
|
|
st "PipelinedOperators"
|
|
blo "57600,34800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*52 (Text
|
|
uid 2443,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "57600,34700,66600,35900"
|
|
st "pipelineCounter"
|
|
blo "57600,35700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*53 (Text
|
|
uid 2444,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "57600,35600,60900,36800"
|
|
st "I_cnt"
|
|
blo "57600,36600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2445,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 2446,0
|
|
text (MLText
|
|
uid 2447,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "57000,37400,76400,39400"
|
|
st "bitNb = counterBitNb ( positive )
|
|
stageNb = pipelineStageNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "bitNb"
|
|
type "positive"
|
|
value "counterBitNb"
|
|
)
|
|
(GiElement
|
|
name "stageNb"
|
|
type "positive"
|
|
value "pipelineStageNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
connectByName 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*54 (Net
|
|
uid 2475,0
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(counterBitNb-1 downto 0)"
|
|
o 3
|
|
suid 20,0
|
|
)
|
|
declText (MLText
|
|
uid 2476,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,9800,26300,11000"
|
|
st "countOut : unsigned(counterBitNb-1 downto 0)"
|
|
)
|
|
)
|
|
*55 (PortIoOut
|
|
uid 2483,0
|
|
shape (CompositeShape
|
|
uid 2484,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 2485,0
|
|
sl 0
|
|
ro 270
|
|
xt "81500,29625,83000,30375"
|
|
)
|
|
(Line
|
|
uid 2486,0
|
|
sl 0
|
|
ro 270
|
|
xt "81000,30000,81500,30000"
|
|
pts [
|
|
"81000,30000"
|
|
"81500,30000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 2487,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2488,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "84000,29350,110300,30750"
|
|
st "countOut : (counterBitNb-1 downto 0)"
|
|
blo "84000,30550"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*56 (Wire
|
|
uid 15,0
|
|
shape (OrthoPolyLine
|
|
uid 16,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,30000,56250,30000"
|
|
pts [
|
|
"17000,30000"
|
|
"56250,30000"
|
|
]
|
|
)
|
|
start &1
|
|
end &49
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 19,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 20,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "17000,28600,20800,30000"
|
|
st "clock"
|
|
blo "17000,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*57 (Wire
|
|
uid 43,0
|
|
shape (OrthoPolyLine
|
|
uid 44,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,42000,22092,42000"
|
|
pts [
|
|
"17000,42000"
|
|
"22092,42000"
|
|
]
|
|
)
|
|
start &3
|
|
end &41
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 47,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 48,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "16000,40600,21800,42000"
|
|
st "reset_N"
|
|
blo "16000,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*58 (Wire
|
|
uid 245,0
|
|
shape (OrthoPolyLine
|
|
uid 246,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50000,32000,56250,34000"
|
|
pts [
|
|
"50000,34000"
|
|
"53000,34000"
|
|
"53000,32000"
|
|
"56250,32000"
|
|
]
|
|
)
|
|
start &36
|
|
end &50
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 251,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 252,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "50000,30600,58600,32000"
|
|
st "resetSynch"
|
|
blo "50000,31800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &23
|
|
)
|
|
*59 (Wire
|
|
uid 873,0
|
|
shape (OrthoPolyLine
|
|
uid 874,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "32000,38000,34000,38000"
|
|
pts [
|
|
"32000,38000"
|
|
"34000,38000"
|
|
]
|
|
)
|
|
end &26
|
|
sat 16
|
|
eat 32
|
|
stc 0
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tg (WTG
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uid 877,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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st "clock"
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blo "30000,37800"
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tm "WireNameMgr"
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)
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)
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on &2
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)
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uid 879,0
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end &28
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ss 0
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sat 32
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eat 32
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stc 0
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sf 1
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si 0
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tg (WTG
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uid 881,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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st "reset"
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blo "29000,41800"
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tm "WireNameMgr"
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)
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)
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on &4
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)
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*61 (Wire
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uid 883,0
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uid 884,0
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va (VaSet
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pts [
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)
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start &29
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end &34
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sat 32
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eat 32
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st 0
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si 0
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tg (WTG
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uid 885,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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st "resetSnch_N"
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blo "39000,33800"
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tm "WireNameMgr"
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)
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)
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on &21
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)
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uid 887,0
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uid 888,0
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va (VaSet
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vasetType 3
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pts [
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"29000,34000"
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)
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end &17
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sat 32
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eat 2
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stc 0
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sf 1
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si 0
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tg (WTG
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uid 891,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 892,0
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va (VaSet
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font "Verdana,12,0"
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)
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st "logic1"
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blo "30000,33800"
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tm "WireNameMgr"
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)
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)
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on &22
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)
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*63 (Wire
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uid 2477,0
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shape (OrthoPolyLine
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uid 2478,0
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va (VaSet
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)
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xt "73750,30000,81000,30000"
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pts [
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"81000,30000"
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)
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start &48
|
|
end &55
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sat 32
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eat 32
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sty 1
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stc 0
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st 0
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sf 1
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si 0
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tg (WTG
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uid 2481,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 2482,0
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va (VaSet
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)
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st "countOut"
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blo "76000,29900"
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tm "WireNameMgr"
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)
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on &54
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)
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grid (Grid
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xySpacing 1000
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xShown 1
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yShown 1
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uid 84,0
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stg "VerticalLayoutStrategy"
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textVec [
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uid 85,0
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va (VaSet
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font "Verdana,8,1"
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)
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st "Package List"
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blo "-3000,800"
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uid 86,0
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va (VaSet
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tm "PackageList"
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)
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)
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compDirBlock (MlTextGroup
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uid 87,0
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stg "VerticalLayoutStrategy"
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textVec [
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uid 88,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "20000,0,30200,1000"
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st "Compiler Directives"
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blo "20000,800"
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)
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*68 (Text
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uid 89,0
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va (VaSet
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isHidden 1
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font "Verdana,8,1"
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)
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st "Pre-module directives:"
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blo "20000,1800"
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)
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*69 (MLText
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uid 90,0
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va (VaSet
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isHidden 1
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)
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xt "20000,2000,32100,4400"
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st "`resetall
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tm "BdCompilerDirectivesTextMgr"
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)
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*70 (Text
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uid 91,0
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va (VaSet
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font "Verdana,8,1"
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st "Post-module directives:"
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blo "20000,4800"
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)
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*71 (MLText
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uid 92,0
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va (VaSet
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isHidden 1
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)
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xt "20000,0,20000,0"
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tm "BdCompilerDirectivesTextMgr"
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)
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*72 (Text
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uid 93,0
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va (VaSet
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isHidden 1
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font "Verdana,8,1"
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st "End-module directives:"
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blo "20000,5800"
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*73 (MLText
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uid 94,0
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va (VaSet
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isHidden 1
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tm "BdCompilerDirectivesTextMgr"
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)
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windowsPaperWidth 761
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windowsPaperHeight 1077
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paperType "A4"
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unixPaperName "A4 (210mm x 297mm)"
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windowsPaperName "A4"
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scale 75
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exportedDirectories [
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]
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)
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pageBreakOrigin "-3000,0"
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va (VaSet
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)
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text (MLText
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va (VaSet
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st "
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Text
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tm "CommentText"
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)
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)
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defaultRequirementText (RequirementText
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va (VaSet
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fg "59904,39936,65280"
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)
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iconMaskName "reqTracerRequirement.msk"
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)
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text (MLText
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va (VaSet
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st "
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Text
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tm "RequirementText"
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visibleWidth 1100
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)
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)
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shape (RectFrame
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va (VaSet
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)
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xt "0,0,20000,20000"
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title (TextAssociate
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ps "TopLeftStrategy"
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text (Text
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va (VaSet
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blo "1000,2000"
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tm "PanelText"
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)
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)
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)
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defaultBlk (Blk
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shape (Rectangle
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va (VaSet
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vasetType 1
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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blo "1700,4200"
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tm "BdLibraryNameMgr"
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*75 (Text
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va (VaSet
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st "<block>"
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blo "1700,5400"
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tm "BlkNameMgr"
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*76 (Text
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va (VaSet
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tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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isHidden 1
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)
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xt "1700,13200,1700,13200"
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|
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header ""
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)
|
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elements [
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defaultMWComponent (MWC
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shape (Rectangle
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va (VaSet
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vasetType 1
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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*78 (Text
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va (VaSet
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*79 (Text
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tm "InstanceNameMgr"
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)
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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)
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header ""
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)
|
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elements [
|
|
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|
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prms (Property
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|
pclass "params"
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pname "params"
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ptn "String"
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visOptions (mwParamsVisibilityOptions
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defaultSaComponent (SaComponent
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shape (Rectangle
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va (VaSet
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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va (VaSet
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blo "1250,4300"
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tm "BdLibraryNameMgr"
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*81 (Text
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va (VaSet
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st "SaComponent"
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tm "CptNameMgr"
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*82 (Text
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va (VaSet
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blo "1250,6300"
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tm "InstanceNameMgr"
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|
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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elements [
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defaultVhdlComponent (VhdlComponent
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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*83 (Text
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va (VaSet
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blo "950,4300"
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|
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*84 (Text
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va (VaSet
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blo "950,5300"
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*85 (Text
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va (VaSet
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|
st "I0"
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blo "950,6300"
|
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tm "InstanceNameMgr"
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)
|
|
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|
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)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
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isHidden 1
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|
)
|
|
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|
)
|
|
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|
|
elements [
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|
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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textVec [
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*86 (Text
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va (VaSet
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blo "450,4300"
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*87 (Text
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va (VaSet
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*88 (Text
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st "I0"
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blo "450,6300"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*89 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*90 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*91 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*92 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*93 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*94 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,6000,4000,7000"
|
|
st "Declarations"
|
|
blo "-3000,6800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,6900,400,7900"
|
|
st "Ports:"
|
|
blo "-3000,7700"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,10800,1800,11800"
|
|
st "Pre User:"
|
|
blo "-3000,11600"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,11700,22600,14100"
|
|
st "-- constant counterBitNb: positive := 20;
|
|
constant pipelineStageNb: positive := 5;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,13700,6000,14700"
|
|
st "Diagram Signals:"
|
|
blo "-3000,14500"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,6000,3000,7000"
|
|
st "Post User:"
|
|
blo "-3000,6800"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-3000,6000,-3000,6000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 20,0
|
|
usingSuid 1
|
|
emptyRow *95 (LEmptyRow
|
|
)
|
|
uid 1406,0
|
|
optionalChildren [
|
|
*96 (RefLabelRowHdr
|
|
)
|
|
*97 (TitleRowHdr
|
|
)
|
|
*98 (FilterRowHdr
|
|
)
|
|
*99 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*100 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*101 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*102 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*103 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*104 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*105 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*106 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*107 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*108 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 1377,0
|
|
)
|
|
*109 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 1379,0
|
|
)
|
|
*110 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 1381,0
|
|
)
|
|
*111 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSnch_N"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 10,0
|
|
)
|
|
)
|
|
uid 1395,0
|
|
)
|
|
*112 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 4
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 1397,0
|
|
)
|
|
*113 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 1399,0
|
|
)
|
|
*114 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(counterBitNb-1 downto 0)"
|
|
o 3
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 2489,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1419,0
|
|
optionalChildren [
|
|
*115 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *116 (MRCItem
|
|
litem &95
|
|
pos 7
|
|
dimension 20
|
|
)
|
|
uid 1421,0
|
|
optionalChildren [
|
|
*117 (MRCItem
|
|
litem &96
|
|
pos 0
|
|
dimension 20
|
|
uid 1422,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &97
|
|
pos 1
|
|
dimension 23
|
|
uid 1423,0
|
|
)
|
|
*119 (MRCItem
|
|
litem &98
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1424,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &108
|
|
pos 0
|
|
dimension 20
|
|
uid 1378,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &109
|
|
pos 3
|
|
dimension 20
|
|
uid 1380,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &110
|
|
pos 1
|
|
dimension 20
|
|
uid 1382,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &111
|
|
pos 4
|
|
dimension 20
|
|
uid 1396,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &112
|
|
pos 5
|
|
dimension 20
|
|
uid 1398,0
|
|
)
|
|
*125 (MRCItem
|
|
litem &113
|
|
pos 6
|
|
dimension 20
|
|
uid 1400,0
|
|
)
|
|
*126 (MRCItem
|
|
litem &114
|
|
pos 2
|
|
dimension 20
|
|
uid 2490,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1425,0
|
|
optionalChildren [
|
|
*127 (MRCItem
|
|
litem &99
|
|
pos 0
|
|
dimension 20
|
|
uid 1426,0
|
|
)
|
|
*128 (MRCItem
|
|
litem &101
|
|
pos 1
|
|
dimension 50
|
|
uid 1427,0
|
|
)
|
|
*129 (MRCItem
|
|
litem &102
|
|
pos 2
|
|
dimension 100
|
|
uid 1428,0
|
|
)
|
|
*130 (MRCItem
|
|
litem &103
|
|
pos 3
|
|
dimension 50
|
|
uid 1429,0
|
|
)
|
|
*131 (MRCItem
|
|
litem &104
|
|
pos 4
|
|
dimension 100
|
|
uid 1430,0
|
|
)
|
|
*132 (MRCItem
|
|
litem &105
|
|
pos 5
|
|
dimension 100
|
|
uid 1431,0
|
|
)
|
|
*133 (MRCItem
|
|
litem &106
|
|
pos 6
|
|
dimension 50
|
|
uid 1432,0
|
|
)
|
|
*134 (MRCItem
|
|
litem &107
|
|
pos 7
|
|
dimension 80
|
|
uid 1433,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1420,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1405,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *135 (LEmptyRow
|
|
)
|
|
uid 1435,0
|
|
optionalChildren [
|
|
*136 (RefLabelRowHdr
|
|
)
|
|
*137 (TitleRowHdr
|
|
)
|
|
*138 (FilterRowHdr
|
|
)
|
|
*139 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*140 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*141 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*142 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*143 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*144 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*145 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*146 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*147 (LogGeneric
|
|
generic (GiElement
|
|
name "counterBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 2600,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1447,0
|
|
optionalChildren [
|
|
*148 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *149 (MRCItem
|
|
litem &135
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 1449,0
|
|
optionalChildren [
|
|
*150 (MRCItem
|
|
litem &136
|
|
pos 0
|
|
dimension 20
|
|
uid 1450,0
|
|
)
|
|
*151 (MRCItem
|
|
litem &137
|
|
pos 1
|
|
dimension 23
|
|
uid 1451,0
|
|
)
|
|
*152 (MRCItem
|
|
litem &138
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1452,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &147
|
|
pos 0
|
|
dimension 20
|
|
uid 2599,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1453,0
|
|
optionalChildren [
|
|
*154 (MRCItem
|
|
litem &139
|
|
pos 0
|
|
dimension 20
|
|
uid 1454,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &141
|
|
pos 1
|
|
dimension 50
|
|
uid 1455,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &142
|
|
pos 2
|
|
dimension 100
|
|
uid 1456,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &143
|
|
pos 3
|
|
dimension 100
|
|
uid 1457,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &144
|
|
pos 4
|
|
dimension 50
|
|
uid 1458,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &145
|
|
pos 5
|
|
dimension 50
|
|
uid 1459,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &146
|
|
pos 6
|
|
dimension 80
|
|
uid 1460,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1448,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1434,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|