Solar panel
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device_config.c
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1
24/*
25 (c) 2018 Microchip Technology Inc. and its subsidiaries.
26
27 Subject to your compliance with these terms, you may use Microchip software and any
28 derivatives exclusively with Microchip products. It is your responsibility to comply with third party
29 license terms applicable to your use of third party software (including open source software) that
30 may accompany Microchip software.
31
32 THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
33 EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY
34 IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS
35 FOR A PARTICULAR PURPOSE.
36
37 IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
38 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
39 WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP
40 HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO
41 THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
42 CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT
43 OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS
44 SOFTWARE.
45*/
46
47// Configuration bits: selected in the GUI
48
49// CONFIG1L
50#pragma config WDT = OFF // Watchdog Timer Enable bit->WDT disabled (control is placed on SWDTEN bit)
51#pragma config STVR = ON // Stack Overflow/Underflow Reset Enable bit->Reset on stack overflow/underflow enabled
52#pragma config XINST = OFF // Extended Instruction Set Enable bit->Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
53#pragma config DEBUG = OFF // Background Debugger Enable bit->Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
54
55// CONFIG1H
56#pragma config CP0 = OFF // Code Protection bit->Program memory is not code-protected
57
58// CONFIG2L
59#pragma config FOSC = HS // Oscillator Selection bits->HS oscillator
60#pragma config FOSC2 = ON // Default/Reset System Clock Select bit->Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
61#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor enabled
62#pragma config IESO = ON // Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit->Two-Speed Start-up enabled
63
64// CONFIG2H
65#pragma config WDTPS = 32768 // Watchdog Timer Postscaler Select bits->1:32768
66
67// CONFIG3L
68#pragma config EASHFT = ON // External Address Bus Shift Enable bit->Address shifting enabled; address on external bus is offset to start at 000000h
69#pragma config MODE = MM // External Memory Bus->Microcontroller mode, external bus disabled
70#pragma config BW = 16 // Data Bus Width Select bit->16-Bit Data Width mode
71#pragma config WAIT = OFF // External Bus Wait Enable bit->Wait states for operations on external memory bus disabled
72
73// CONFIG3H
74#pragma config CCP2MX = ON // ECCP2 MUX bit->ECCP2/P2A is multiplexed with RC1
75#pragma config ECCPMX = ON // ECCP MUX bit->ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
76#pragma config ETHLED = ON // Ethernet LED Enable bit->RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled