diff --git a/306-controller_interface.X/main.c b/306-controller_interface.X/main.c index d81327c..56c7aa7 100644 --- a/306-controller_interface.X/main.c +++ b/306-controller_interface.X/main.c @@ -9,7 +9,6 @@ void main(void) { // Initialize the device SYSTEM_Initialize(); - // Disable the Global Interrupts // INTERRUPT_GlobalInterruptDisable(); @@ -21,6 +20,7 @@ void main(void) Factory_init(); Factory_build(); Factory_start(); + //WWDT_SoftEnable(); // let the XF timers handling become the TMR0 interrupt handler // this means that the XF timers are always decremented when the @@ -33,6 +33,7 @@ void main(void) while (1) { //handle the next event if there is any in the queue + WWDT_TimerClear(); XF_executeOnce(); //maybe sleep a short while to save energy } diff --git a/306-controller_interface.X/mcc_generated_files/device_config.c b/306-controller_interface.X/mcc_generated_files/device_config.c index 1e3bf51..24d7219 100644 --- a/306-controller_interface.X/mcc_generated_files/device_config.c +++ b/306-controller_interface.X/mcc_generated_files/device_config.c @@ -73,8 +73,8 @@ #pragma config XINST = OFF // Extended Instruction Set Enable bit->Extended Instruction Set and Indexed Addressing Mode disabled // CONFIG3L -#pragma config WDTCPS = WDTCPS_31 // WDT Period selection bits->Divider ratio 1:65536; software control of WDTPS -#pragma config WDTE = OFF // WDT operating mode->WDT Disabled; SWDTEN is ignored +#pragma config WDTCPS = WDTCPS_6 // WDT Period selection bits->Divider ratio 1:2048 +#pragma config WDTE = SWDTEN // WDT operating mode->WDT enabled/disabled by SWDTEN bit // CONFIG3H #pragma config WDTCWS = WDTCWS_7 // WDT Window Select bits->window always open (100%); software control; keyed access not required diff --git a/306-controller_interface.X/mcc_generated_files/mcc.c b/306-controller_interface.X/mcc_generated_files/mcc.c index e2cbde5..6c698bd 100644 --- a/306-controller_interface.X/mcc_generated_files/mcc.c +++ b/306-controller_interface.X/mcc_generated_files/mcc.c @@ -53,6 +53,7 @@ void SYSTEM_Initialize(void) PMD_Initialize(); PIN_MANAGER_Initialize(); OSCILLATOR_Initialize(); + WWDT_Initialize(); TMR0_Initialize(); ECAN_Initialize(); } @@ -92,6 +93,50 @@ void PMD_Initialize(void) } +void WWDT_Initialize(void) +{ + // Initializes the WWDT to the default states configured in the MCC GUI + WDTCON0 = WDTCPS; + WDTCON1 = WDTCWS|WDTCCS; + +} + +void WWDT_SoftEnable(void) +{ + // WWDT software enable. + WDTCON0bits.SEN=1; +} + +void WWDT_SoftDisable(void) +{ + // WWDT software disable. + WDTCON0bits.SEN=0; +} + +bool WWDT_TimeOutStatusGet(void) +{ + // Return the status of WWDT time out reset. + return (PCON0bits.nRWDT); +} + +bool WWDT_WindowViolationStatusGet(void) +{ + // Return the status of WWDT window violation reset. + return (PCON0bits.nWDTWV); +} + +void WWDT_TimerClear(void) +{ + // Disable the interrupt,read back the WDTCON0 reg for arming, + // clearing the WWDT and enable the interrupt. + uint8_t readBack=0; + + bool state = GIE; + GIE = 0; + readBack = WDTCON0; + CLRWDT(); + GIE = state; +} /** End of File */ diff --git a/306-controller_interface.X/mcc_generated_files/mcc.h b/306-controller_interface.X/mcc_generated_files/mcc.h index f681b38..117f4c8 100644 --- a/306-controller_interface.X/mcc_generated_files/mcc.h +++ b/306-controller_interface.X/mcc_generated_files/mcc.h @@ -57,6 +57,9 @@ #include "tmr0.h" #include "ecan.h" +#define WDTCWS 7 +#define WDTCCS 48 +#define WDTCPS 12 /** @@ -98,6 +101,84 @@ void OSCILLATOR_Initialize(void); */ void PMD_Initialize(void); +/** + * @Param + none + * @Returns + none + * @Description + Initializes the WWDT to the default states configured in the + * MCC GUI + * @Example + WWDT_Initialize(); + */ +void WWDT_Initialize(void); + + +/** + * @Param + none + * @Returns + none + * @Description + Enable the WWDT by setting the SEN bit. + * @Example + WWDT_SoftEnable(); + */ +void WWDT_SoftEnable(void); + +/** + * @Param + none + * @Returns + none + * @Description + Disable the WWDT by clearing the SEN bit. + * @Example + WWDT_SoftDisable(); + */ +void WWDT_SoftDisable(void); + +/** + * @Param + none + * @Returns + none + * @Description + Disable the interrupt, arm the WWDT by reading back the WDTCON0 register + * clear the WWDT and enable the interrupt. + * @Example + WWDT_TimerClear(); + */ +void WWDT_TimerClear(void); + +/** + * @Param + none + * @Returns + High --> WWDT reset has not occurred. + * Low --> WWDT reset has occurred. + * @Description + Returns the status of whether the WWDT reset has occurred or not. + * @Example + if(WWDT_TimeOutStatusGet()) + */ +bool WWDT_TimeOutStatusGet(void); + +/** + * @Param + none + * @Returns + High --> WWDT window violation reset has not occurred. + * Low --> WWDT window violation reset has occurred. + * @Description + Returns the status of, whether the WWDT window violation + * reset has occurred or not. + * @Example + if(WWDT_WindowViolationStatusGet()) + */ +bool WWDT_WindowViolationStatusGet(void); + #endif /* MCC_H */ /** diff --git a/306-controller_interface.X/nbproject/configurations.xml b/306-controller_interface.X/nbproject/configurations.xml index 9a8cbd2..d515866 100644 --- a/306-controller_interface.X/nbproject/configurations.xml +++ b/306-controller_interface.X/nbproject/configurations.xml @@ -224,6 +224,7 @@ + diff --git a/306-controller_interface.X/ss22ep.mc3 b/306-controller_interface.X/ss22ep.mc3 index 2f25ff4..cecac1b 100644 --- a/306-controller_interface.X/ss22ep.mc3 +++ b/306-controller_interface.X/ss22ep.mc3 @@ -1948,7 +1948,7 @@ - {"dataArray":[{"DMA Channels":{"data":{"isDisable":"true","options":"--NONE--","text":"DMA CHANNEL1","value":"false"},"id":"DMA Channels_rowCount_0"},"Src Module":{"data":{"isDisable":"true","options":"--NONE--,MEMORY,ECAN,TMR0","text":"--NONE--","value":"--NONE--"},"id":"Src Module_rowCount_0"},"Src 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Trigger":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"data":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"id":"Start Trigger_rowCount_0"},"Abort Trigger":{"data":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"id":"Abort Trigger_rowCount_0","Abort Trigger":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"}}},{"DMA Channels":{"data":{"isDisable":"true","options":"--NONE--","text":"DMA CHANNEL2","value":"false"},"id":"DMA Channels_rowCount_1"},"Src Module":{"data":{"isDisable":"true","options":"--NONE--,TMR0,MEMORY,ECAN","text":"--NONE--","value":"--NONE--"},"id":"Src Module_rowCount_1"},"Src Region":{"data":{"isDisable":"true","options":"SFR#disabled,GPR#enabled,Program Flash#enabled,Data EEPROM#enabled","text":"GPR","value":"GPR"},"id":"Src Region_rowCount_1"},"Src SFR":{"Src SFR":{"isDisable":"true","options":"","text":"","value":""},"data":{"isDisable":"true","options":"","text":"","value":""},"id":"Src SFR_rowCount_1"},"Src VarName":{"data":{"isDisable":"true","options":"","text":"SrcVarName1","value":"SrcVarName1"},"Src VarName":{"isDisable":"true","options":"","text":"SrcVarName1","value":"SrcVarName1"},"id":"Src VarName_rowCount_1"},"Src VarSize":{"data":{"isDisable":"true","options":"","text":"10","value":"10"},"id":"Src VarSize_rowCount_1","Src VarSize":{"isDisable":"true","options":"","text":"10","value":"10"}},"Src Address":{"data":{"isDisable":"true","options":"","text":"Enter Address1","value":"Enter Address1"},"id":"Src Address_rowCount_1","Src Address":{"isDisable":"true","options":"","text":"Enter Address1","value":"Enter Address1"}},"Src Mode":{"Src Mode":{"isDisable":"true","options":"decremented,incremented,unchanged","text":"unchanged","value":"unchanged"},"data":{"isDisable":"true","options":"decremented,incremented,unchanged","text":"unchanged","value":"unchanged"},"id":"Src Mode_rowCount_1"},"Src Message Size":{"data":{"isDisable":"true","options":"","text":"1","value":"1"},"Src Message Size":{"isDisable":"true","options":"","text":"1","value":"1"},"id":"Src Message Size_rowCount_1"},"Dst Module":{"data":{"isDisable":"true","options":"--NONE--,TMR0,MEMORY,ECAN","text":"--NONE--","value":"--NONE--"},"id":"Dst Module_rowCount_1"},"Dst Region":{"data":{"isDisable":"true","options":"SFR,GPR","text":"GPR","value":"GPR"},"id":"Dst Region_rowCount_1"},"Dst SFR":{"Dst SFR":{"isDisable":"true","options":"","text":"","value":""},"data":{"isDisable":"true","options":"","text":"","value":""},"id":"Dst SFR_rowCount_1"},"Dst VarName":{"data":{"isDisable":"true","options":"","text":"DstVarName1","value":"DstVarName1"},"Dst VarName":{"isDisable":"true","options":"","text":"DstVarName1","value":"DstVarName1"},"id":"Dst VarName_rowCount_1"},"Dst VarSize":{"data":{"isDisable":"true","options":"","text":"10","value":"10"},"id":"Dst VarSize_rowCount_1","Dst VarSize":{"isDisable":"true","options":"","text":"10","value":"10"}},"Dst Mode":{"data":{"isDisable":"true","options":"decremented,incremented,unchanged","text":"unchanged","value":"unchanged"},"Dst Mode":{"isDisable":"true","options":"decremented,incremented,unchanged","text":"unchanged","value":"unchanged"},"id":"Dst Mode_rowCount_1"},"Dst Message Size":{"data":{"isDisable":"true","options":"","text":"1","value":"1"},"Dst Message Size":{"isDisable":"true","options":"","text":"1","value":"1"},"id":"Dst Message Size_rowCount_1"},"Start Trigger":{"Start Trigger":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"data":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"id":"Start Trigger_rowCount_1"},"Abort Trigger":{"data":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"},"id":"Abort Trigger_rowCount_1","Abort Trigger":{"isDisable":"true","options":"AD,ADT,CAN_ERRIF,CAN_IRXIF,CAN_RXB0IF\/FIFOIF,CAN_RXB1IF\/RXBnIF,CAN_TXB0IF,CAN_TXB1IF,CAN_TXB2IF\/TXBnIF,CAN_WAKIF,CCP1,CCP2,CCP3,CCP4,CLC1,CLC2,CLC3,CLC4,CMP1,CMP2,CRC,CSW,CWG1,CWG2,CWG3,DMA1A,DMA1DCNT,DMA1OR,DMA1SCNT,DMA2A,DMA2DCNT,DMA2OR,DMA2SCNT,I2C1,I2C1E,I2C1RX,I2C1TX,I2C2,I2C2E,I2C2RX,I2C2TX,INT0,INT1,INT2,IOC,LVD,NCO,NVM,None,OSF,SCAN,SMT1,SMT1PRA,SMT1PWA,SMT2,SMT2PRA,SMT2PWA,SPI1,SPI1RX,SPI1TX,TMR0,TMR1,TMR1G,TMR2,TMR3,TMR3G,TMR4,TMR5,TMR5G,TMR6,U1,U1E,U1RX,U1TX,U2,U2E,U2RX,U2TX,ZCD","text":"None","value":"None"}}}],"type":"tableDynamicControls","key":"dmaTable"} @@ -16508,7 +16508,7 @@ - 31 + 38 @@ -16604,11 +16604,11 @@ - WDTCPS_31 + WDTCPS_6 - OFF + SWDTEN @@ -16976,7 +16976,7 @@ - 2.11406 + 0.06606 @@ -17159,54 +17159,34 @@ Window delay time 87.5% - + - main.c - cae37ae3b36cf22e97e106633433f5c00a66dd5d38ec353eb67fbbb0d88bde4d - - - mcc_generated_files\device_config.c - 39a6d1181ef5eab59c7dde2c52a9ea889465d4da43262200f3322abc45e77739 + mcc_generated_files\mcc.h + 7dd04034216f3c639fcfb88387572f995d54189bb8fb587a3401371ec2651c65 mcc_generated_files\device_config.h 89c6172ff575ce515b93f2fbc85dcedc2978e58a8e0e1fbdc52e42511ae3bc05 - - mcc_generated_files\ecan.c - ea62f50d319e1e537d7632774728ad6a779f442e896d043dbdea8066d028a6c6 - - - mcc_generated_files\ecan.h - aa9a50aae81bab76b876ea6123777af7d6a6d0a58fe953be27e8b88776395b2e - - - mcc_generated_files\interrupt_manager.c - df04edcd2c7d85ef90a8dbe4e46f1b1c9487b872153f4f2321249a4ce0d9635f - mcc_generated_files\interrupt_manager.h 9c2f1ae45f2ac887bb3e8b3763e1a394a6a22ffe4e9ae1c20c336fe6f12da1aa - - mcc_generated_files\mcc.c - cc9ed44843b509879e6a3f676b561ecde91e1df88d855cf7eca77e1afc8920ca - - - mcc_generated_files\mcc.h - a2db7e36e878f686c2bf0c2ef586ef1c6570fa2f27119b4be7b52af6403091a4 - mcc_generated_files\memory.c 17fb4759c4719b77287f6c4be48edfbcf117b5b8398b771c434f23aceac256e0 - mcc_generated_files\memory.h - fbbca4e9d7ce92ddcc637d82b694a1f5cbefa75710a8a18bb1dc9ab5161f0924 + mcc_generated_files\tmr0.h + 6661ab783aae9f11e952805f9bca14209ec06551939552123056eefd5524fff8 - mcc_generated_files\pin_manager.c - 04b16a3d3fcbbb333ee6fb545a405b76aba47ef3935be548bf2b8165c43c5654 + main.c + cae37ae3b36cf22e97e106633433f5c00a66dd5d38ec353eb67fbbb0d88bde4d + + + mcc_generated_files\device_config.c + ac2a2ad923df635be3b193de8878c95bc16cfb8c91d37b98c4c1a4a1e0e6b990 mcc_generated_files\pin_manager.h @@ -17217,8 +17197,28 @@ e0b4d075e819024ae77ea60a2c01182fdca45b783980cb50358d0a614736339d - mcc_generated_files\tmr0.h - 6661ab783aae9f11e952805f9bca14209ec06551939552123056eefd5524fff8 + mcc_generated_files\pin_manager.c + 04b16a3d3fcbbb333ee6fb545a405b76aba47ef3935be548bf2b8165c43c5654 + + + mcc_generated_files\ecan.c + ea62f50d319e1e537d7632774728ad6a779f442e896d043dbdea8066d028a6c6 + + + mcc_generated_files\mcc.c + a1b3e2d6ddc04b8a97973fcb818a7243d9723f4763c2c496b4b2eb1aa06ad645 + + + mcc_generated_files\interrupt_manager.c + df04edcd2c7d85ef90a8dbe4e46f1b1c9487b872153f4f2321249a4ce0d9635f + + + mcc_generated_files\memory.h + fbbca4e9d7ce92ddcc637d82b694a1f5cbefa75710a8a18bb1dc9ab5161f0924 + + + mcc_generated_files\ecan.h + aa9a50aae81bab76b876ea6123777af7d6a6d0a58fe953be27e8b88776395b2e \ No newline at end of file