diff --git a/src/element.typ b/src/element.typ
index 3bf0e17..85e040d 100644
--- a/src/element.typ
+++ b/src/element.typ
@@ -11,5 +11,10 @@
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
+#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
+#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
+#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
 
 #import "elements/group.typ": group
\ No newline at end of file
diff --git a/src/elements/logic/iec_and.typ b/src/elements/logic/iec_and.typ
new file mode 100644
index 0000000..515b128
--- /dev/null
+++ b/src/elements/logic/iec_and.typ
@@ -0,0 +1,70 @@
+#import "@preview/cetz:0.3.2": draw
+// #import "iec_gate.typ" as iec-gate
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-and
+#let gate-iec-and(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $amp$,
+  )
+
+}
+
+/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-nand
+#let gate-iec-nand(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  ),
+) = {
+  gate-iec-and(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug,
+  )
+}
\ No newline at end of file
diff --git a/src/elements/logic/iec_buf.typ b/src/elements/logic/iec_buf.typ
new file mode 100644
index 0000000..478b4e3
--- /dev/null
+++ b/src/elements/logic/iec_buf.typ
@@ -0,0 +1,68 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+
+/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
+///
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-buf
+#let gate-iec-buf(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: "1",
+  )
+}
+
+/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-not
+#let gate-iec-not(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false,
+  ),
+) = {
+  gate-iec-buf(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
+    debug: debug,
+  )
+}
diff --git a/src/elements/logic/iec_gate.typ b/src/elements/logic/iec_gate.typ
new file mode 100644
index 0000000..3334d11
--- /dev/null
+++ b/src/elements/logic/iec_gate.typ
@@ -0,0 +1,148 @@
+#import "@preview/cetz:0.3.2": draw, coordinate
+#import "../ports.typ": add-ports, add-port
+#import "../element.typ"
+
+#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
+  let (x, y) = bl
+  let (width, height) = (tr.at(0) - x, tr.at(1) - y)
+
+  let t = (x + width / 2, y + height)
+  let b = (x + width / 2, y)
+
+  let f = draw.group(
+    name: id,
+    {
+      draw.merge-path(
+        inset: 0.5em,
+        fill: fill,
+        stroke: stroke,
+        name: id + "-path",
+        close: true,
+        {
+          draw.line(bl, tl, tr, br)
+        },
+      )
+
+      draw.content(
+        (x + width / 2, y + height / 2),
+        padding: 0.5em,
+        align(center)[*$ symbol $*],
+      )
+
+      draw.anchor("north", t) 
+      draw.anchor("south", b)
+    },
+  )
+  return (f, tl, tr, br, bl)
+}
+
+
+/// Draws a logic gate. This function is also available as `element.iec-gate()`
+///
+/// - draw-shape (function): see #doc-ref("element.elmt")
+/// - x (number, dictionary): see #doc-ref("element.elmt")
+/// - y (number, dictionary): see #doc-ref("element.elmt")
+/// - w (number): see #doc-ref("element.elmt")
+/// - h (number): see #doc-ref("element.elmt")
+/// - inputs (int): The number of inputs
+/// - fill (none, color): see #doc-ref("element.elmt")
+/// - stroke (stroke): see #doc-ref("element.elmt")
+/// - id (str): see #doc-ref("element.elmt")
+/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
+/// - inverted-radius (number): The radius of inverted ports dot
+/// - debug (dictionary): see #doc-ref("element.elmt")
+/// - symbol (str): The symbol to display at the center of the gate
+#let iec-gate(
+  draw-shape: default-draw-shape,
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  inverted-radius: 0.1,
+  debug: (
+    ports: false
+  ),
+  symbol: "",
+) = draw.get-ctx(ctx => {
+  let width = w
+  let height = h
+
+  let x = x
+  let y = y
+  if x == none { panic("Parameter x must be set") }
+  if y == none { panic("Parameter y must be set") }
+  if w == none { panic("Parameter w must be set") }
+  if h == none { panic("Parameter h must be set") }
+
+  if (type(x) == dictionary) {
+    let offset = x.rel
+    let to = x.to
+    let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
+    x = to-pos.at(0)
+  }
+  
+  if (type(y) == dictionary) {
+    let from = y.from
+    let to = y.to
+    
+    let dy
+    if to == "out" {
+      dy = height / 2
+    } else {
+      dy = height * (i + 0.5) / inputs
+    }
+    
+    let (ctx, from-pos) = coordinate.resolve(ctx, from)
+    y = from-pos.at(1) + dy - height
+  }
+
+  let tl = (x, y + height)
+  let tr = (x + width, y + height)
+  let br = (x + width, y)
+  let bl = (x, y)
+
+  // Workaround because CeTZ needs to have all draw functions in the body
+  let func = {}
+  (func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
+  func
+
+  let space = 100% / inputs
+  for i in range(inputs) {
+    let pct = (i + 0.5) * space
+    let a = (tl, pct, bl)
+    let b = (tr, pct, br)
+    let int-name = id + "i" + str(i)
+    draw.intersections(
+      int-name,
+      func,
+      draw.hide(draw.line(a, b))
+    )
+    let port-name = "in" + str(i)
+    let port-pos = int-name + ".0"
+    if inverted == "all" or port-name in inverted {
+      draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke)
+      port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
+    }
+    add-port(
+      id, "west",
+      (id: port-name), port-pos,
+      debug: debug.ports
+    )
+  }
+
+  let out-pos = id + ".east"
+  if inverted == "all" or "out" in inverted {
+    draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
+    out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
+  }
+  add-port(
+    id, "east",
+    (id: "out"), out-pos,
+    debug: debug.ports
+  )
+})
\ No newline at end of file
diff --git a/src/elements/logic/iec_or.typ b/src/elements/logic/iec_or.typ
new file mode 100644
index 0000000..653106a
--- /dev/null
+++ b/src/elements/logic/iec_or.typ
@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-or
+#let gate-iec-or(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $>= 1$,
+  )
+}
+
+/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-nor
+#let gate-iec-nor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  gate-iec-or(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}
\ No newline at end of file
diff --git a/src/elements/logic/iec_xor.typ b/src/elements/logic/iec_xor.typ
new file mode 100644
index 0000000..8a63dc0
--- /dev/null
+++ b/src/elements/logic/iec_xor.typ
@@ -0,0 +1,67 @@
+#import "@preview/cetz:0.3.2": draw
+#import "iec_gate.typ" as iec-gate
+
+/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-xor
+#let gate-iec-xor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  iec-gate.iec-gate(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: inverted,
+    debug: debug,
+    symbol: $= 1$,
+  )
+}
+
+/// Draws an IEC-NXOR gate. This function is also available as `element.iec-gate-nxor()`
+/// 
+/// For parameters, see #doc-ref("gates.iec-gate")
+/// #examples.gate-iec-nxor
+#let gate-iec-nxor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  inputs: 2,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  inverted: (),
+  debug: (
+    ports: false
+  )
+) = {
+  gate-iec-xor(
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    inputs: inputs,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
+    debug: debug
+  )
+}
\ No newline at end of file
diff --git a/src/gates.typ b/src/gates.typ
index 85ba178..9b3ea2b 100644
--- a/src/gates.typ
+++ b/src/gates.typ
@@ -2,4 +2,9 @@
 #import "elements/logic/and.typ": gate-and, gate-nand
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
-#import "elements/logic/buf.typ": gate-buf, gate-not
\ No newline at end of file
+#import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/iec_gate.typ": iec-gate
+#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
+#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
+#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
+#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor