65 lines
1.4 KiB
YAML
65 lines
1.4 KiB
YAML
|
structures:
|
||
|
|
main:
|
||
|
|
bits: 32
|
||
|
|
ranges:
|
||
|
|
31-8:
|
||
|
|
name: '-'
|
||
|
|
7-6:
|
||
|
|
name: code
|
||
|
|
5-4:
|
||
|
|
name: params
|
||
|
|
description: parameter
|
||
|
|
values:
|
||
|
|
00: unsigned integer
|
||
|
|
01: signed integer
|
||
|
|
10: unsigned float
|
||
|
|
11: signed float
|
||
|
|
3-0:
|
||
|
|
name: values
|
||
|
|
depends-on: 7-6
|
||
|
|
values:
|
||
|
|
00:
|
||
|
|
description: increment register
|
||
|
|
structure: valuesIncrReg
|
||
|
|
01:
|
||
|
|
description: add registers
|
||
|
|
structure: valuesAddReg
|
||
|
|
10:
|
||
|
|
description: add immediate value and register
|
||
|
|
structure: valuesAddImmReg
|
||
|
|
11:
|
||
|
|
description: right shift register by value
|
||
|
|
structure: valuesShiftReg
|
||
|
|
valuesIncrReg:
|
||
|
|
bits: 4
|
||
|
|
ranges:
|
||
|
|
3-0:
|
||
|
|
name: register address
|
||
|
|
valuesAddReg:
|
||
|
|
bits: 4
|
||
|
|
ranges:
|
||
|
|
3-2:
|
||
|
|
name: r1
|
||
|
|
description: first register address
|
||
|
|
1-0:
|
||
|
|
name: r2
|
||
|
|
description: second register address
|
||
|
|
valuesAddImmReg:
|
||
|
|
bits: 4
|
||
|
|
ranges:
|
||
|
|
3-2:
|
||
|
|
name: val
|
||
|
|
description: immediate value
|
||
|
|
1-0:
|
||
|
|
name: r1
|
||
|
|
description: register address
|
||
|
|
valuesShiftReg:
|
||
|
|
bits: 4
|
||
|
|
ranges:
|
||
|
|
3-2:
|
||
|
|
name: shift
|
||
|
|
description: shift amount
|
||
|
|
1-0:
|
||
|
|
name: r1
|
||
|
|
description: register address
|