mirror of
https://github.com/Klagarge/Cursor.git
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1658 lines
20 KiB
Plaintext
1658 lines
20 KiB
Plaintext
|
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 55,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 77,0
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optionalChildren [
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|
*2 (RefLabelRowHdr
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|
)
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||
|
*3 (TitleRowHdr
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||
|
)
|
||
|
*4 (FilterRowHdr
|
||
|
)
|
||
|
*5 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
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||
|
)
|
||
|
*6 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
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||
|
)
|
||
|
*7 (GroupColHdr
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|
tm "GroupColHdrMgr"
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||
|
)
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||
|
*8 (NameColHdr
|
||
|
tm "NameColHdrMgr"
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|
)
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||
|
*9 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
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||
|
)
|
||
|
*10 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
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||
|
)
|
||
|
*11 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
|
||
|
)
|
||
|
*12 (InitColHdr
|
||
|
tm "InitColHdrMgr"
|
||
|
)
|
||
|
*13 (EolColHdr
|
||
|
tm "EolColHdrMgr"
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||
|
)
|
||
|
*14 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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|
n "A0"
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|
t "std_ulogic"
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|
o 1
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|
suid 46,0
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|
)
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|
)
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|
uid 606,0
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|
)
|
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|
*15 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
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||
|
n "busy"
|
||
|
t "std_ulogic"
|
||
|
o 6
|
||
|
suid 47,0
|
||
|
)
|
||
|
)
|
||
|
uid 608,0
|
||
|
)
|
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*16 (LogPort
|
||
|
port (LogicalPort
|
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|
m 1
|
||
|
decl (Decl
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|
n "clock"
|
||
|
t "std_ulogic"
|
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|
o 7
|
||
|
suid 48,0
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|
)
|
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|
)
|
||
|
uid 610,0
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|
)
|
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|
*17 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
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|
n "CS_n"
|
||
|
t "std_ulogic"
|
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|
o 2
|
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|
suid 49,0
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|
)
|
||
|
)
|
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|
uid 612,0
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||
|
)
|
||
|
*18 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "data"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(dataBitNb-1 DOWNTO 0)"
|
||
|
o 8
|
||
|
suid 50,0
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|
)
|
||
|
)
|
||
|
uid 614,0
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||
|
)
|
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*19 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "reset"
|
||
|
t "std_ulogic"
|
||
|
o 9
|
||
|
suid 51,0
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||
|
)
|
||
|
)
|
||
|
uid 616,0
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||
|
)
|
||
|
*20 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "RST_n"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 52,0
|
||
|
)
|
||
|
)
|
||
|
uid 618,0
|
||
|
)
|
||
|
*21 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "SCL"
|
||
|
t "std_ulogic"
|
||
|
o 4
|
||
|
suid 53,0
|
||
|
)
|
||
|
)
|
||
|
uid 620,0
|
||
|
)
|
||
|
*22 (LogPort
|
||
|
port (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "send"
|
||
|
t "std_ulogic"
|
||
|
o 10
|
||
|
suid 54,0
|
||
|
)
|
||
|
)
|
||
|
uid 622,0
|
||
|
)
|
||
|
*23 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "SI"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 55,0
|
||
|
)
|
||
|
)
|
||
|
uid 624,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 90,0
|
||
|
optionalChildren [
|
||
|
*24 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
)
|
||
|
emptyMRCItem *25 (MRCItem
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||
|
litem &1
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||
|
pos 10
|
||
|
dimension 20
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||
|
)
|
||
|
uid 92,0
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|
optionalChildren [
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|
*26 (MRCItem
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|
litem &2
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|
pos 0
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||
|
dimension 20
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|
uid 93,0
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||
|
)
|
||
|
*27 (MRCItem
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||
|
litem &3
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||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 94,0
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||
|
)
|
||
|
*28 (MRCItem
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||
|
litem &4
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 95,0
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||
|
)
|
||
|
*29 (MRCItem
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||
|
litem &14
|
||
|
pos 0
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||
|
dimension 20
|
||
|
uid 607,0
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||
|
)
|
||
|
*30 (MRCItem
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||
|
litem &15
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||
|
pos 1
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||
|
dimension 20
|
||
|
uid 609,0
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||
|
)
|
||
|
*31 (MRCItem
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||
|
litem &16
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 611,0
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|
)
|
||
|
*32 (MRCItem
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||
|
litem &17
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||
|
pos 3
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||
|
dimension 20
|
||
|
uid 613,0
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||
|
)
|
||
|
*33 (MRCItem
|
||
|
litem &18
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 615,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &19
|
||
|
pos 5
|
||
|
dimension 20
|
||
|
uid 617,0
|
||
|
)
|
||
|
*35 (MRCItem
|
||
|
litem &20
|
||
|
pos 6
|
||
|
dimension 20
|
||
|
uid 619,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &21
|
||
|
pos 7
|
||
|
dimension 20
|
||
|
uid 621,0
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||
|
)
|
||
|
*37 (MRCItem
|
||
|
litem &22
|
||
|
pos 8
|
||
|
dimension 20
|
||
|
uid 623,0
|
||
|
)
|
||
|
*38 (MRCItem
|
||
|
litem &23
|
||
|
pos 9
|
||
|
dimension 20
|
||
|
uid 625,0
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||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
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||
|
cellColor "0,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
textAngle 90
|
||
|
)
|
||
|
uid 96,0
|
||
|
optionalChildren [
|
||
|
*39 (MRCItem
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||
|
litem &5
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 97,0
|
||
|
)
|
||
|
*40 (MRCItem
|
||
|
litem &7
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 98,0
|
||
|
)
|
||
|
*41 (MRCItem
|
||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 99,0
|
||
|
)
|
||
|
*42 (MRCItem
|
||
|
litem &9
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 100,0
|
||
|
)
|
||
|
*43 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 101,0
|
||
|
)
|
||
|
*44 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 102,0
|
||
|
)
|
||
|
*45 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 103,0
|
||
|
)
|
||
|
*46 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 104,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 91,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 76,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *47 (LEmptyRow
|
||
|
)
|
||
|
uid 106,0
|
||
|
optionalChildren [
|
||
|
*48 (RefLabelRowHdr
|
||
|
)
|
||
|
*49 (TitleRowHdr
|
||
|
)
|
||
|
*50 (FilterRowHdr
|
||
|
)
|
||
|
*51 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*52 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*53 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*54 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*55 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*56 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*57 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*58 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*59 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "clockFrequency"
|
||
|
type "real"
|
||
|
value "100.0E6"
|
||
|
)
|
||
|
uid 155,0
|
||
|
)
|
||
|
*60 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "dataBitNb"
|
||
|
type "positive"
|
||
|
value "9"
|
||
|
)
|
||
|
uid 345,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 118,0
|
||
|
optionalChildren [
|
||
|
*61 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *62 (MRCItem
|
||
|
litem &47
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 120,0
|
||
|
optionalChildren [
|
||
|
*63 (MRCItem
|
||
|
litem &48
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 121,0
|
||
|
)
|
||
|
*64 (MRCItem
|
||
|
litem &49
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 122,0
|
||
|
)
|
||
|
*65 (MRCItem
|
||
|
litem &50
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 123,0
|
||
|
)
|
||
|
*66 (MRCItem
|
||
|
litem &59
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 156,0
|
||
|
)
|
||
|
*67 (MRCItem
|
||
|
litem &60
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 346,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 124,0
|
||
|
optionalChildren [
|
||
|
*68 (MRCItem
|
||
|
litem &51
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 125,0
|
||
|
)
|
||
|
*69 (MRCItem
|
||
|
litem &53
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 126,0
|
||
|
)
|
||
|
*70 (MRCItem
|
||
|
litem &54
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 127,0
|
||
|
)
|
||
|
*71 (MRCItem
|
||
|
litem &55
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 128,0
|
||
|
)
|
||
|
*72 (MRCItem
|
||
|
litem &56
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 129,0
|
||
|
)
|
||
|
*73 (MRCItem
|
||
|
litem &57
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 130,0
|
||
|
)
|
||
|
*74 (MRCItem
|
||
|
litem &58
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 131,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 119,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 105,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable " "
|
||
|
value " "
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@serializer_tester\\interface.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@serializer_tester\\interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@serializer_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdSerializer_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "11.11.2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Mon"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Monday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "11"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "lcdSerializer_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "silvan.zahno"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "11.11.2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "WE6996"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "07:37:47"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE6996"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Lcd_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/ElN/Libraries/Lcd_test/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "11"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "lcdSerializer_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Nov"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "November"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@serializer_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdSerializer_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ADMS"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "07:37:47"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "lcdSerializer_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "silvan.zahno"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2019.2 (Build 5)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2019"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "19"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "VhdlLangMgr"
|
||
|
uid 75,0
|
||
|
optionalChildren [
|
||
|
*75 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*76 (CptPort
|
||
|
uid 556,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 557,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "58625,5250,59375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 558,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 559,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "58300,7000,59700,9400"
|
||
|
st "A0"
|
||
|
ju 2
|
||
|
blo "59500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 560,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,2400,59500,3200"
|
||
|
st "A0 : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "A0"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 46,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*77 (CptPort
|
||
|
uid 561,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 562,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "26625,5250,27375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 563,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 564,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "26300,7000,27700,10800"
|
||
|
st "busy"
|
||
|
ju 2
|
||
|
blo "27500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 565,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,6400,59500,7200"
|
||
|
st "busy : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "busy"
|
||
|
t "std_ulogic"
|
||
|
o 6
|
||
|
suid 47,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*78 (CptPort
|
||
|
uid 566,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 567,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "30625,5250,31375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 568,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 569,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "30300,7000,31700,10800"
|
||
|
st "clock"
|
||
|
ju 2
|
||
|
blo "31500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 570,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,7200,59500,8000"
|
||
|
st "clock : OUT std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 7
|
||
|
suid 48,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*79 (CptPort
|
||
|
uid 571,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 572,0
|
||
|
ro 180
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54625,5250,55375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 573,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 574,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "54300,7000,55700,11100"
|
||
|
st "CS_n"
|
||
|
ju 2
|
||
|
blo "55500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 575,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,3200,59500,4000"
|
||
|
st "CS_n : IN std_ulogic ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "CS_n"
|
||
|
t "std_ulogic"
|
||
|
o 2
|
||
|
suid 49,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*80 (CptPort
|
||
|
uid 576,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 577,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "22625,5250,23375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 578,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 579,0
|
||
|
ro 270
|
||
|
va (VaSet
|
||
|
font "Verdana,12,0"
|
||
|
)
|
||
|
xt "22300,7000,23700,10700"
|
||
|
st "data"
|
||
|
ju 2
|
||
|
blo "23500,7000"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 580,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,8000,74500,8800"
|
||
|
st "data : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;
|
||
|
"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "data"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(dataBitNb-1 DOWNTO 0)"
|
||
|
o 8
|
||
|
suid 50,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*81 (CptPort
|
||
|
uid 581,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 582,0
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "32625,5250,33375,6000"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 583,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
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shape (Diamond
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "65535,65535,65535"
|
||
|
bg "0,0,0"
|
||
|
)
|
||
|
xt "0,0,750,750"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
va (VaSet
|
||
|
)
|
||
|
xt "0,750,4300,1950"
|
||
|
st "Buffer0"
|
||
|
blo "0,1750"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 3
|
||
|
decl (Decl
|
||
|
n "Buffer0"
|
||
|
t "std_ulogic_vector"
|
||
|
b "(15 DOWNTO 0)"
|
||
|
o 0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
DeclarativeBlock *91 (SymDeclBlock
|
||
|
uid 1,0
|
||
|
stg "SymDeclLayoutStrategy"
|
||
|
declLabel (Text
|
||
|
uid 2,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "42000,0,49400,1200"
|
||
|
st "Declarations"
|
||
|
blo "42000,1000"
|
||
|
)
|
||
|
portLabel (Text
|
||
|
uid 3,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "42000,1200,45700,2400"
|
||
|
st "Ports:"
|
||
|
blo "42000,2200"
|
||
|
)
|
||
|
externalLabel (Text
|
||
|
uid 4,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "42000,10400,45200,11600"
|
||
|
st "User:"
|
||
|
blo "42000,11400"
|
||
|
)
|
||
|
internalLabel (Text
|
||
|
uid 6,0
|
||
|
va (VaSet
|
||
|
isHidden 1
|
||
|
font "Verdana,9,1"
|
||
|
)
|
||
|
xt "42000,0,50200,1200"
|
||
|
st "Internal User:"
|
||
|
blo "42000,1000"
|
||
|
)
|
||
|
externalText (MLText
|
||
|
uid 5,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "44000,11600,44000,11600"
|
||
|
tm "SyDeclarativeTextMgr"
|
||
|
)
|
||
|
internalText (MLText
|
||
|
uid 7,0
|
||
|
va (VaSet
|
||
|
isHidden 1
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "42000,0,42000,0"
|
||
|
tm "SyDeclarativeTextMgr"
|
||
|
)
|
||
|
)
|
||
|
lastUid 625,0
|
||
|
activeModelName "Symbol:GEN"
|
||
|
)
|