mirror of
https://github.com/Klagarge/Cursor.git
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1949 lines
23 KiB
Plaintext
1949 lines
23 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "24.1"
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appVersion "2009.2 (Build 10)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 24,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 21,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "A0"
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t "std_ulogic"
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o 5
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suid 1,0
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)
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)
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uid 126,0
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)
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*15 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 3,0
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)
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)
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uid 130,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "CS_n"
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t "std_ulogic"
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o 6
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suid 4,0
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)
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)
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uid 132,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 2
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suid 7,0
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)
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)
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uid 138,0
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)
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*18 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "RST_n"
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t "std_ulogic"
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o 7
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suid 8,0
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)
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)
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uid 140,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "SCL"
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t "std_ulogic"
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o 4
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suid 9,0
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)
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)
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uid 142,0
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)
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*20 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "SI"
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t "std_ulogic"
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o 3
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suid 10,0
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)
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)
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uid 144,0
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)
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*21 (LogPort
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port (LogicalPort
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decl (Decl
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n "data"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 8
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suid 11,0
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)
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)
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uid 398,0
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)
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*22 (LogPort
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port (LogicalPort
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decl (Decl
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n "send"
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||
|
t "std_ulogic"
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|
o 9
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suid 17,0
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)
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)
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uid 478,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "busy"
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t "std_ulogic"
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|
o 10
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suid 19,0
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)
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)
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uid 508,0
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)
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]
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)
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pdm (PhysicalDM
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|
displayShortBounds 1
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editShortBounds 1
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uid 34,0
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optionalChildren [
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*24 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *25 (MRCItem
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litem &1
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pos 10
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dimension 20
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)
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uid 36,0
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optionalChildren [
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*26 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 37,0
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)
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*27 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 38,0
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)
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*28 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 39,0
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)
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*29 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 127,0
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)
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*30 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 131,0
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)
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*31 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 133,0
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)
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*32 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 139,0
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)
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*33 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 141,0
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)
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*34 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 143,0
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)
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*35 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 145,0
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)
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*36 (MRCItem
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litem &21
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pos 7
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dimension 20
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uid 399,0
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||
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)
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*37 (MRCItem
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||
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litem &22
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||
|
pos 8
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dimension 20
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|
uid 479,0
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)
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*38 (MRCItem
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litem &23
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pos 9
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dimension 20
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uid 509,0
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||
|
)
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||
|
]
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||
|
)
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||
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sheetCol (SheetCol
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||
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 40,0
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optionalChildren [
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*39 (MRCItem
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||
|
litem &5
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||
|
pos 0
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||
|
dimension 20
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||
|
uid 41,0
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||
|
)
|
||
|
*40 (MRCItem
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||
|
litem &7
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||
|
pos 1
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||
|
dimension 50
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||
|
uid 42,0
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||
|
)
|
||
|
*41 (MRCItem
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||
|
litem &8
|
||
|
pos 2
|
||
|
dimension 100
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||
|
uid 43,0
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||
|
)
|
||
|
*42 (MRCItem
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||
|
litem &9
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||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 44,0
|
||
|
)
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||
|
*43 (MRCItem
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||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
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||
|
uid 45,0
|
||
|
)
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||
|
*44 (MRCItem
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||
|
litem &11
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||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 46,0
|
||
|
)
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||
|
*45 (MRCItem
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||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 47,0
|
||
|
)
|
||
|
*46 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
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||
|
uid 48,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 35,0
|
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|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 20,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *47 (LEmptyRow
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||
|
)
|
||
|
uid 50,0
|
||
|
optionalChildren [
|
||
|
*48 (RefLabelRowHdr
|
||
|
)
|
||
|
*49 (TitleRowHdr
|
||
|
)
|
||
|
*50 (FilterRowHdr
|
||
|
)
|
||
|
*51 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*52 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*53 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*54 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*55 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*56 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*57 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*58 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*59 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "baudRateDivide"
|
||
|
type "integer"
|
||
|
value "2"
|
||
|
)
|
||
|
uid 170,0
|
||
|
)
|
||
|
*60 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "dataBitNb"
|
||
|
type "positive"
|
||
|
value "9"
|
||
|
)
|
||
|
uid 197,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 62,0
|
||
|
optionalChildren [
|
||
|
*61 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *62 (MRCItem
|
||
|
litem &47
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 64,0
|
||
|
optionalChildren [
|
||
|
*63 (MRCItem
|
||
|
litem &48
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 65,0
|
||
|
)
|
||
|
*64 (MRCItem
|
||
|
litem &49
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 66,0
|
||
|
)
|
||
|
*65 (MRCItem
|
||
|
litem &50
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 67,0
|
||
|
)
|
||
|
*66 (MRCItem
|
||
|
litem &59
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 171,0
|
||
|
)
|
||
|
*67 (MRCItem
|
||
|
litem &60
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 198,0
|
||
|
)
|
||
|
]
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||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 68,0
|
||
|
optionalChildren [
|
||
|
*68 (MRCItem
|
||
|
litem &51
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 69,0
|
||
|
)
|
||
|
*69 (MRCItem
|
||
|
litem &53
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 70,0
|
||
|
)
|
||
|
*70 (MRCItem
|
||
|
litem &54
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 71,0
|
||
|
)
|
||
|
*71 (MRCItem
|
||
|
litem &55
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 72,0
|
||
|
)
|
||
|
*72 (MRCItem
|
||
|
litem &56
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 73,0
|
||
|
)
|
||
|
*73 (MRCItem
|
||
|
litem &57
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 74,0
|
||
|
)
|
||
|
*74 (MRCItem
|
||
|
litem &58
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 75,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 63,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 49,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable " "
|
||
|
value " "
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcd@serializer\\symbol.sb.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcd@serializer\\symbol.sb.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "ADC"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcd@serializer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcdSerializer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "12.07.2013"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "ven."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "vendredi"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "12"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "lcdSerializer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE3673"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "Lcd"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_Concatenation"
|
||
|
value "$HDS_PROJECT_DIR/../libs/SPI/concat"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_HdsLintPlugin"
|
||
|
value "$HDS_PROJECT_DIR/../libs/SPI/designcheck"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/$DESIGN_NAME/Lcd/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "07"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "lcdSerializer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "juil."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "juillet"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcd@serializer\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "D:\\Labs\\LCD\\..\\Libs\\Lcd\\hds\\lcdSerializer\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ADMS"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "15:35:23"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "lcdSerializer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2009.2 (Build 10)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2013"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "13"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "VhdlLangMgr"
|
||
|
uid 19,0
|
||
|
optionalChildren [
|
||
|
*75 (SymbolBody
|
||
|
uid 8,0
|
||
|
optionalChildren [
|
||
|
*76 (CptPort
|
||
|
uid 76,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 77,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54000,5625,54750,6375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 78,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 79,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "50800,5400,53000,6600"
|
||
|
st "A0"
|
||
|
ju 2
|
||
|
blo "53000,6400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 80,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-1800,17500,-1000"
|
||
|
st "A0 : OUT std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "A0"
|
||
|
t "std_ulogic"
|
||
|
o 5
|
||
|
suid 1,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*77 (CptPort
|
||
|
uid 86,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 87,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "37250,9625,38000,10375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 88,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 89,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "39000,9400,42400,10600"
|
||
|
st "clock"
|
||
|
blo "39000,10400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 90,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-5000,17500,-4200"
|
||
|
st "clock : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 3,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*78 (CptPort
|
||
|
uid 91,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 92,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54000,9625,54750,10375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 93,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 94,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "49600,9400,53000,10600"
|
||
|
st "CS_n"
|
||
|
ju 2
|
||
|
blo "53000,10400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 95,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-1000,17500,-200"
|
||
|
st "CS_n : OUT std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "CS_n"
|
||
|
t "std_ulogic"
|
||
|
o 6
|
||
|
suid 4,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*79 (CptPort
|
||
|
uid 106,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 107,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "37250,11625,38000,12375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 108,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 109,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "39000,11400,42300,12600"
|
||
|
st "reset"
|
||
|
blo "39000,12400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 110,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-4200,17500,-3400"
|
||
|
st "reset : IN std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
decl (Decl
|
||
|
n "reset"
|
||
|
t "std_ulogic"
|
||
|
o 2
|
||
|
suid 7,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*80 (CptPort
|
||
|
uid 111,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 112,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54000,7625,54750,8375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 113,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 114,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "49000,7400,53000,8600"
|
||
|
st "RST_n"
|
||
|
ju 2
|
||
|
blo "53000,8400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 115,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-200,17500,600"
|
||
|
st "RST_n : OUT std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "RST_n"
|
||
|
t "std_ulogic"
|
||
|
o 7
|
||
|
suid 8,0
|
||
|
)
|
||
|
)
|
||
|
)
|
||
|
*81 (CptPort
|
||
|
uid 116,0
|
||
|
ps "OnEdgeStrategy"
|
||
|
shape (Triangle
|
||
|
uid 117,0
|
||
|
ro 90
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "54000,3625,54750,4375"
|
||
|
)
|
||
|
tg (CPTG
|
||
|
uid 118,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
||
|
stg "RightVerticalLayoutStrategy"
|
||
|
f (Text
|
||
|
uid 119,0
|
||
|
va (VaSet
|
||
|
font "Verdana,9,0"
|
||
|
)
|
||
|
xt "50200,3400,53000,4600"
|
||
|
st "SCL"
|
||
|
ju 2
|
||
|
blo "53000,4400"
|
||
|
tm "CptPortNameMgr"
|
||
|
)
|
||
|
)
|
||
|
dt (MLText
|
||
|
uid 120,0
|
||
|
va (VaSet
|
||
|
font "Courier New,8,0"
|
||
|
)
|
||
|
xt "2000,-2600,17500,-1800"
|
||
|
st "SCL : OUT std_ulogic ;"
|
||
|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "SCL"
|
||
|
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