mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
267 lines
20 KiB
Plaintext
267 lines
20 KiB
Plaintext
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Performing generation for single diagram...
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Checking which design units need saving
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Incrementally generating HDL...
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.
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tb_struct.vhg
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Generation completed successfully.
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--------------------------------------------------------
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Comparing HDL files with compiled files ...
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Current working directory is C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Scripts
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Executing data preparation plug-in for 10.7c
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Performing compile...
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Library Cursor_test
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Model Technology ModelSim SE vmap 10.7c Lib Mapping Utility 2018.08 Aug 18 2018
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vmap -c
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Copying C:/eda/MentorGraphics/modelsim/win32/../modelsim.ini to modelsim.ini
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Writing temporary output file "C:/Users/remi/AppData/Local/Temp/Files0".
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Start time: 21:06:29 on Dec 20,2021
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vcom -work Cursor_test -nologo -2008 -f C:/Users/remi/AppData/Local/Temp/Files0
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-- Loading package STANDARD
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-- Compiling entity cursor_tb
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Loading package NUMERIC_STD
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** Error: C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Prefs/../Cursor_test/hdl/cursor_tb_struct.vhg(14): (vcom-1598) Library "cursor" not found.
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** Note: C:/Users/remi/OneDrive/Documents/Cours/05-HEVS/S1fb/electricity/1-EIN/project/cursor/HDLdesigner/Cursor/Prefs/../Cursor_test/hdl/cursor_tb_struct.vhg(17): VHDL Compiler exiting
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End time: 21:06:29 on Dec 20,2021, Elapsed time: 0:00:00
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Errors: 1, Warnings: 0
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child process exited abnormally
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Failed during ModelSim compile - Error executing "C:/eda/MentorGraphics/modelsim/win32/vcom -work "Cursor_test" -nologo -2008 -f C:/Users/remi/AppData/Local/Temp/Files0"
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Compiled 2 file(s) in 1 compiler invocation(s) with 2 failure(s)
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Data preparation step completed, check transcript...
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---------------------------------------------------------------------------------
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Performing hierarchical generation through components...
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Checking which design units need saving
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Incrementally generating HDL...
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.
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Cursor/cursorCircuit
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cursorcircuit_entity.vhg
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Cursor/Position
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\position_entity.vhg
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Cursor/Encoder
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\encoder_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\encoder_encoder.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Cursor/Compteur
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteur_entity.vhg
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Cursor/compteurUpDownRsyncAll
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_entity.vhg'.
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"compteurupdownrsyncall_entity.vhg",line 24: Error, 'integer' requires 0 index values.
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gates/bufferUlogic
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\bufferulogic_entity.vhg
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Cursor/cpt4bit
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg'.
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"cpt4bit_entity.vhg",line 23: Error, 'integer' requires 0 index values.
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Cursor/cpt1bit
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt1bit_entity.vhg
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sequential/DFF
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Sequential\hdl\dff_entity.vhg
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gates/xor2
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\xor2_entity.vhg
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gates/and2
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\and2_entity.vhg
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gates/inverter
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\inverter_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt1bit_struct.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_struct.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_entity.vhg'.
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"cpt4bit_entity.vhg",line 23: Error, 'integer' requires 0 index values.
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cpt4bit_struct.vhg'.
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"cpt4bit_struct.vhg",line 19: Error, attempt to parse architecture body for 'cpt4bit' when a dependency has errors
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or before parsing the entity declaration.
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\compteurupdownrsyncall_struct.vhg
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Error: The block diagram interface is inconsistent with the interface on the parent block.
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Use the Update Interface command.
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gates/or2
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\or2_entity.vhg
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Cursor/convertissor_position
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\convertissor_position_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\convertissor_position_entity.vhg'.
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"convertissor_position_entity.vhg",line 20: Error, 'integer' requires 0 index values.
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Cursor/Button
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_entity.vhg
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Cursor/button_position
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_position_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_position_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\button_button.vhg
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Error: The block diagram interface is inconsistent with the interface on the parent block.
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Use the Update Interface command.
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Cannot have a slice/element when connected to a Port.
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For input ports, please use the entire array with no slice/elements and rip a slice/element from this Signal.
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For output ports, please use HDL text to assign the slice/element to an alternative output Signal.
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The following port Signals have slices :
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button4(3)
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Error: Signal 'button4' connects to Signal 'button', this would produce invalid HDL.
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Error: Signal 'dbus0' connects to Signal 'button', this would produce invalid HDL.
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Cursor/Main
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\main_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\main_entity.vhg'.
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"main_entity.vhg",line 25: Error, 'testlinenb' is not declared.
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Cursor/move
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\move_fsm.vhg'.
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"move_fsm.vhg",line 102: Error, type error at 'power_cruse'. Needed type 'std_ulogic_vector'.
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"move_fsm.vhg",line 106: Error, type error at 'power_deceleration'. Needed type 'std_ulogic_vector'.
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Cursor/set_position
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\set_position_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\set_position_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Cursor/process_cruse
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_cruse_fsm.vhg'.
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"process_cruse_fsm.vhg",line 113: Error, cannot use a string literal in a scalar expression.
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"process_cruse_fsm.vhg",line 117: Error, cannot use a string literal in a scalar expression.
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"process_cruse_fsm.vhg",line 120: Error, cannot use a string literal in a scalar expression.
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"process_cruse_fsm.vhg",line 124: Error, cannot use a string literal in a scalar expression.
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Cursor/process_deceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_deceleration_fsm.vhg'.
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"process_deceleration_fsm.vhg",line 103: Error, cannot use a string literal in a scalar expression.
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"process_deceleration_fsm.vhg",line 108: Error, cannot use a string literal in a scalar expression.
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Cursor/selector_acceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_acceleration_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_acceleration_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Cursor/selector_cruse
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_cruse_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_cruse_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Cursor/selector_deceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_deceleration_entity.vhg
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\selector_deceleration_fsm.vhg
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Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
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(Hint: A default value is required for all combinatorial signals (and the internal signals
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generated for registered outputs) to avoid implied latches).
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Cursor/process_acceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\process_acceleration_entity.vhg
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Cursor/side_acceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\side_acceleration_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\side_acceleration_entity.vhg'.
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"side_acceleration_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values.
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Cursor/enable_acceleration
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\enable_acceleration_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\enable_acceleration_entity.vhg'.
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"enable_acceleration_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values.
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Cursor/accelerator
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\accelerator_entity.vhg
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-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\accelerator_entity.vhg'.
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"accelerator_entity.vhg",line 15: Error, 'std_ulogic' requires 0 index values.
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Cursor/Driver
|
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_entity.vhg
|
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|
||
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Cursor/Counter_Controller
|
||
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Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\counter_controller_entity.vhg
|
||
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Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\counter_controller_fsm.vhg
|
||
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Warning: Ignoring implicit loopback set on State 'reset_counter' with true condition leaving it.
|
||
|
|
Warning: Ignoring implicit loopback set on State 'add_start' with true condition leaving it.
|
||
|
|
Warning: Ignoring implicit loopback set on State 'waiting' with true condition leaving it.
|
||
|
|
Warning: Ignoring implicit loopback set on State 'add_end' with true condition leaving it.
|
||
|
|
Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
|
||
|
|
(Hint: A default value is required for all combinatorial signals (and the internal signals
|
||
|
|
generated for registered outputs) to avoid implied latches).
|
||
|
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|
||
|
|
sequential/counterEnableResetSync
|
||
|
|
Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Sequential\hdl\counterenableresetsync_entity.vhg
|
||
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|
|
||
|
|
gates/logic1
|
||
|
|
Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Libs\Gates\hdl\logic1_entity.vhg
|
||
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|
||
|
|
Cursor/Motor_side
|
||
|
|
Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\motor_side_entity.vhg
|
||
|
|
Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\motor_side_fsm.vhg
|
||
|
|
Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
|
||
|
|
(Hint: A default value is required for all combinatorial signals (and the internal signals
|
||
|
|
generated for registered outputs) to avoid implied latches).
|
||
|
|
|
||
|
|
Cursor/PWM
|
||
|
|
Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\pwm_entity.vhg
|
||
|
|
Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\pwm_fsm.vhg
|
||
|
|
Warning: Default values for one or more Combinatorial signals have not been specified in the Signals Table.
|
||
|
|
(Hint: A default value is required for all combinatorial signals (and the internal signals
|
||
|
|
generated for registered outputs) to avoid implied latches).
|
||
|
|
Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_drivert.vhg
|
||
|
|
-- Reading file 'C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\driver_drivert.vhg'.
|
||
|
|
"driver_drivert.vhg",line 132: Error, type error at 'countOut'. Needed type 'std_ulogic_vector'.
|
||
|
|
Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor\hdl\cursorcircuit_studentversion.vhg
|
||
|
|
Error: The following component instances are out of date with respect to their symbol interface:-
|
||
|
|
I3, I2
|
||
|
|
Use Update Interface command to resolve differences.
|
||
|
|
Error: Signal 'reset' connects to Signal 'rst', this would produce invalid HDL.
|
||
|
|
Error: Signal 'clock' connects to Signal 'clk', this would produce invalid HDL.
|
||
|
|
|
||
|
|
Cursor_test/cursor_tester
|
||
|
|
Generating entity C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tester_entity.vhg
|
||
|
|
Generating architecture C:\Users\remi\OneDrive\Documents\Cours\05-HEVS\S1fb\electricity\1-EIN\project\cursor\HDLdesigner\Cursor\Prefs\..\Cursor_test\hdl\cursor_tb_struct.vhg
|
||
|
|
|
||
|
|
Generation completed with errors.
|
||
|
|
--------------------------------------------------------
|
||
|
|
|
||
|
|
|