Klagarge/Cursor
1
0
Fork 0
mirror of https://github.com/Klagarge/Cursor.git synced 2025-06-25 20:02:31 +00:00
Code Issues Activity

try to correct 1

Browse Source
This commit is contained in:
Rémi Heredero
2021-12-21 14:29:44 +01:00
parent f8fe936949
commit 39617b48f4
8 changed files with 153 additions and 171 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
Cursor_test/hds/cursor_tb/struct.bd
View File

@ -78,23 +78,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.info"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.user"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "appl"
@ -114,11 +114,11 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
)
(vvPair
variable "d_logical"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
)
(vvPair
variable "date"
@ -162,7 +162,7 @@ value "struct"
)
(vvPair
variable "graphical_source_author"
value "Simon"
value "remi"
)
(vvPair
variable "graphical_source_date"
@ -174,11 +174,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "PC-SDM"
value "MARVIN"
)
(vvPair
variable "graphical_source_time"
value "13:58:56"
value "14:28:55"
)
(vvPair
variable "group"
@ -186,7 +186,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "PC-SDM"
value "MARVIN"
)
(vvPair
variable "language"
@ -222,11 +222,11 @@ value "d
)
(vvPair
variable "p"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
)
(vvPair
variable "package_name"
@ -302,7 +302,7 @@ value "struct"
)
(vvPair
variable "time"
value "13:58:56"
value "14:28:55"
)
(vvPair
variable "unit"
@ -310,7 +310,7 @@ value "cursor_tb"
)
(vvPair
variable "user"
value "Simon"
value "remi"
)
(vvPair
variable "version"
@ -1266,7 +1266,7 @@ m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 DOWNTO 0)"
b "(1 TO testLineNb)"
o 21
suid 8,0
)
@ -1552,9 +1552,10 @@ blo "40000,45500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "button4"
t "std_uLogic"
t "std_ulogic"
o 1
suid 16,0
)
@ -2530,8 +2531,8 @@ tm "BdCompilerDirectivesTextMgr"
]
associable 1
)
windowSize "0,0,1715,1119"
viewArea "-8938,13684,103005,88288"
windowSize "0,0,1537,960"
viewArea "-8900,13700,104983,86084"
cachedDiagramExtent "-7000,-1400,102000,93000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\ipp://ipp.hevs.ch\\PREA309_HPLJP3005DN,winspool,"
@ -2558,7 +2559,7 @@ boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,19000"
lastUid 5517,0
lastUid 5570,0
defaultCommentText (CommentText
shape (Rectangle
layer 0