1
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mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-26 11:13:27 +00:00

Merge pull request #2 from Klagarge/main_block

Main block
This commit is contained in:
Rémi Heredero 2021-12-14 15:13:42 +01:00 committed by GitHub
commit 67f2fe7508
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GPG Key ID: 4AEE18F83AFDEB23
54 changed files with 104055 additions and 489 deletions

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@ -21,7 +21,7 @@ appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 12,0
suid 74,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
@ -68,22 +68,22 @@ n "button"
t "unsigned"
b "(3 DOWNTO 0)"
o 2
suid 1,0
suid 63,0
)
)
uid 111,0
uid 809,0
)
*15 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "clock"
t "std_ulogic"
n "clk"
t "unsigned"
o 3
suid 2,0
suid 64,0
)
)
uid 113,0
uid 811,0
)
*16 (LogPort
port (LogicalPort
@ -93,10 +93,10 @@ n "Position"
t "unsigned"
b "(15 DOWNTO 0)"
o 1
suid 3,0
suid 65,0
)
)
uid 115,0
uid 813,0
)
*17 (LogPort
port (LogicalPort
@ -107,10 +107,10 @@ n "Power"
t "unsigned"
b "(7 DOWNTO 0)"
o 8
suid 4,0
suid 66,0
)
)
uid 117,0
uid 815,0
)
*18 (LogPort
port (LogicalPort
@ -120,46 +120,44 @@ decl (Decl
n "RaZ"
t "std_ulogic"
o 9
suid 5,0
suid 67,0
)
)
uid 119,0
uid 817,0
)
*19 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "reset"
t "std_ulogic"
n "rst"
t "unsigned"
o 4
suid 6,0
suid 68,0
)
)
uid 121,0
uid 819,0
)
*20 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "sensor1"
t "std_uLogic"
o 5
suid 7,0
suid 69,0
)
)
uid 123,0
uid 821,0
)
*21 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "sensor2"
t "std_uLogic"
o 6
suid 8,0
suid 70,0
)
)
uid 125,0
uid 823,0
)
*22 (LogPort
port (LogicalPort
@ -169,36 +167,34 @@ decl (Decl
n "SideL"
t "std_ulogic"
o 10
suid 9,0
suid 71,0
)
)
uid 127,0
uid 825,0
)
*23 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "testMode"
t "std_uLogic"
o 7
suid 10,0
suid 72,0
)
)
uid 129,0
uid 827,0
)
*24 (LogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 TO testLineNb)"
o 11
suid 11,0
suid 73,0
)
)
uid 131,0
uid 829,0
)
*25 (LogPort
port (LogicalPort
@ -208,10 +204,10 @@ decl (Decl
n "unlock"
t "std_ulogic"
o 12
suid 12,0
suid 74,0
)
)
uid 133,0
uid 831,0
)
]
)
@ -265,75 +261,75 @@ uid 155,0
)
*31 (MRCItem
litem &14
pos 1
pos 0
dimension 20
uid 112,0
uid 810,0
)
*32 (MRCItem
litem &15
pos 8
pos 1
dimension 20
uid 114,0
uid 812,0
)
*33 (MRCItem
litem &16
pos 0
pos 2
dimension 20
uid 116,0
uid 814,0
)
*34 (MRCItem
litem &17
pos 5
pos 3
dimension 20
uid 118,0
uid 816,0
)
*35 (MRCItem
litem &18
pos 6
pos 4
dimension 20
uid 120,0
uid 818,0
)
*36 (MRCItem
litem &19
pos 9
pos 5
dimension 20
uid 122,0
uid 820,0
)
*37 (MRCItem
litem &20
pos 2
pos 6
dimension 20
uid 124,0
uid 822,0
)
*38 (MRCItem
litem &21
pos 3
pos 7
dimension 20
uid 126,0
uid 824,0
)
*39 (MRCItem
litem &22
pos 7
pos 8
dimension 20
uid 128,0
uid 826,0
)
*40 (MRCItem
litem &23
pos 4
pos 9
dimension 20
uid 130,0
uid 828,0
)
*41 (MRCItem
litem &24
pos 10
dimension 20
uid 132,0
uid 830,0
)
*42 (MRCItem
litem &25
pos 11
dimension 20
uid 134,0
uid 832,0
)
]
)
@ -564,23 +560,23 @@ VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hdl"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface.info"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface.user"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds"
)
(vvPair
variable "appl"
@ -600,15 +596,15 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\@main"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\@main"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\Main"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\Main"
)
(vvPair
variable "date"
value "07.12.2021"
value "14.12.2021"
)
(vvPair
variable "day"
@ -620,7 +616,7 @@ value "mardi"
)
(vvPair
variable "dd"
value "07"
value "14"
)
(vvPair
variable "entity_name"
@ -644,11 +640,11 @@ value "interface"
)
(vvPair
variable "graphical_source_author"
value "remi"
value "Simon"
)
(vvPair
variable "graphical_source_date"
value "07.12.2021"
value "14.12.2021"
)
(vvPair
variable "graphical_source_group"
@ -656,11 +652,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "MARVIN"
value "PC-SDM"
)
(vvPair
variable "graphical_source_time"
value "08:20:45"
value "14:20:05"
)
(vvPair
variable "group"
@ -668,7 +664,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "MARVIN"
value "PC-SDM"
)
(vvPair
variable "language"
@ -700,11 +696,11 @@ value "d
)
(vvPair
variable "p"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\@main\\interface"
)
(vvPair
variable "p_logical"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\Main\\interface"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor\\hds\\Main\\interface"
)
(vvPair
variable "package_name"
@ -732,7 +728,7 @@ value "interface"
)
(vvPair
variable "time"
value "08:20:45"
value "14:20:05"
)
(vvPair
variable "unit"
@ -740,7 +736,7 @@ value "Main"
)
(vvPair
variable "user"
value "remi"
value "Simon"
)
(vvPair
variable "version"
@ -767,10 +763,10 @@ optionalChildren [
uid 8,0
optionalChildren [
*76 (CptPort
uid 51,0
uid 749,0
ps "OnEdgeStrategy"
shape (Triangle
uid 52,0
uid 750,0
ro 90
va (VaSet
vasetType 1
@ -779,11 +775,11 @@ fg "0,65535,0"
xt "14250,38625,15000,39375"
)
tg (CPTG
uid 53,0
uid 751,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 54,0
uid 752,0
va (VaSet
font "Verdana,12,0"
)
@ -794,12 +790,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 55,0
uid 753,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3200,66500,4000"
st "button : IN unsigned (3 DOWNTO 0) ;"
st "button : IN unsigned (3 DOWNTO 0) ;
"
)
thePort (LogicalPort
lang 11
@ -808,60 +805,61 @@ n "button"
t "unsigned"
b "(3 DOWNTO 0)"
o 2
suid 1,0
suid 63,0
)
)
)
*77 (CptPort
uid 56,0
uid 754,0
ps "OnEdgeStrategy"
shape (Triangle
uid 57,0
uid 755,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,62625,15000,63375"
xt "14250,58625,15000,59375"
)
tg (CPTG
uid 58,0
uid 756,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 59,0
uid 757,0
va (VaSet
font "Verdana,12,0"
)
xt "16000,62300,19800,63700"
st "clock"
blo "16000,63500"
xt "16000,58300,18400,59700"
st "clk"
blo "16000,59500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 60,0
uid 758,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4000,61000,4800"
st "clock : IN std_ulogic ;"
xt "44000,4000,60000,4800"
st "clk : IN unsigned ;
"
)
thePort (LogicalPort
lang 11
decl (Decl
n "clock"
t "std_ulogic"
n "clk"
t "unsigned"
o 3
suid 2,0
suid 64,0
)
)
)
*78 (CptPort
uid 61,0
uid 759,0
ps "OnEdgeStrategy"
shape (Triangle
uid 62,0
uid 760,0
ro 90
va (VaSet
vasetType 1
@ -870,11 +868,11 @@ fg "0,65535,0"
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 63,0
uid 761,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 64,0
uid 762,0
va (VaSet
font "Verdana,12,0"
)
@ -885,12 +883,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 65,0
uid 763,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2400,67000,3200"
st "Position : IN unsigned (15 DOWNTO 0) ;"
st "Position : IN unsigned (15 DOWNTO 0) ;
"
)
thePort (LogicalPort
lang 11
@ -899,15 +898,15 @@ n "Position"
t "unsigned"
b "(15 DOWNTO 0)"
o 1
suid 3,0
suid 65,0
)
)
)
*79 (CptPort
uid 66,0
uid 764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 67,0
uid 765,0
ro 90
va (VaSet
vasetType 1
@ -916,11 +915,11 @@ fg "0,65535,0"
xt "45000,59625,45750,60375"
)
tg (CPTG
uid 68,0
uid 766,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 69,0
uid 767,0
va (VaSet
font "Verdana,12,0"
)
@ -932,12 +931,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 70,0
uid 768,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8000,66500,8800"
st "Power : OUT unsigned (7 DOWNTO 0) ;"
st "Power : OUT unsigned (7 DOWNTO 0) ;
"
)
thePort (LogicalPort
lang 11
@ -947,15 +947,15 @@ n "Power"
t "unsigned"
b "(7 DOWNTO 0)"
o 8
suid 4,0
suid 66,0
)
)
)
*80 (CptPort
uid 71,0
uid 769,0
ps "OnEdgeStrategy"
shape (Triangle
uid 72,0
uid 770,0
ro 270
va (VaSet
vasetType 1
@ -964,11 +964,11 @@ fg "0,65535,0"
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 73,0
uid 771,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 74,0
uid 772,0
va (VaSet
font "Verdana,12,0"
)
@ -979,12 +979,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 75,0
uid 773,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8800,61000,9600"
st "RaZ : OUT std_ulogic ;"
st "RaZ : OUT std_ulogic ;
"
)
thePort (LogicalPort
lang 11
@ -993,60 +994,61 @@ decl (Decl
n "RaZ"
t "std_ulogic"
o 9
suid 5,0
suid 67,0
)
)
)
*81 (CptPort
uid 76,0
uid 774,0
ps "OnEdgeStrategy"
shape (Triangle
uid 77,0
uid 775,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,63625,15000,64375"
xt "14250,59625,15000,60375"
)
tg (CPTG
uid 78,0
uid 776,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 79,0
uid 777,0
va (VaSet
font "Verdana,12,0"
)
xt "16000,63300,20100,64700"
st "reset"
blo "16000,64500"
xt "16000,59300,18500,60700"
st "rst"
blo "16000,60500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 80,0
uid 778,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4800,61000,5600"
st "reset : IN std_ulogic ;"
xt "44000,4800,60000,5600"
st "rst : IN unsigned ;
"
)
thePort (LogicalPort
lang 11
decl (Decl
n "reset"
t "std_ulogic"
n "rst"
t "unsigned"
o 4
suid 6,0
suid 68,0
)
)
)
*82 (CptPort
uid 81,0
uid 779,0
ps "OnEdgeStrategy"
shape (Triangle
uid 82,0
uid 780,0
ro 90
va (VaSet
vasetType 1
@ -1055,11 +1057,11 @@ fg "0,65535,0"
xt "14250,53625,15000,54375"
)
tg (CPTG
uid 83,0
uid 781,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 84,0
uid 782,0
va (VaSet
font "Verdana,12,0"
)
@ -1070,28 +1072,28 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 85,0
uid 783,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5600,61000,6400"
st "sensor1 : IN std_uLogic ;"
st "sensor1 : IN std_uLogic ;
"
)
thePort (LogicalPort
lang 11
decl (Decl
n "sensor1"
t "std_uLogic"
o 5
suid 7,0
suid 69,0
)
)
)
*83 (CptPort
uid 86,0
uid 784,0
ps "OnEdgeStrategy"
shape (Triangle
uid 87,0
uid 785,0
ro 90
va (VaSet
vasetType 1
@ -1100,11 +1102,11 @@ fg "0,65535,0"
xt "14250,51625,15000,52375"
)
tg (CPTG
uid 88,0
uid 786,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 89,0
uid 787,0
va (VaSet
font "Verdana,12,0"
)
@ -1115,28 +1117,28 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 90,0
uid 788,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6400,61000,7200"
st "sensor2 : IN std_uLogic ;"
st "sensor2 : IN std_uLogic ;
"
)
thePort (LogicalPort
lang 11
decl (Decl
n "sensor2"
t "std_uLogic"
o 6
suid 8,0
suid 70,0
)
)
)
*84 (CptPort
uid 91,0
uid 789,0
ps "OnEdgeStrategy"
shape (Triangle
uid 92,0
uid 790,0
ro 90
va (VaSet
vasetType 1
@ -1145,11 +1147,11 @@ fg "0,65535,0"
xt "45000,63625,45750,64375"
)
tg (CPTG
uid 93,0
uid 791,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 94,0
uid 792,0
va (VaSet
font "Verdana,12,0"
)
@ -1161,12 +1163,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 95,0
uid 793,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9600,61000,10400"
st "SideL : OUT std_ulogic ;"
st "SideL : OUT std_ulogic ;
"
)
thePort (LogicalPort
lang 11
@ -1175,15 +1178,15 @@ decl (Decl
n "SideL"
t "std_ulogic"
o 10
suid 9,0
suid 71,0
)
)
)
*85 (CptPort
uid 96,0
uid 794,0
ps "OnEdgeStrategy"
shape (Triangle
uid 97,0
uid 795,0
ro 90
va (VaSet
vasetType 1
@ -1192,11 +1195,11 @@ fg "0,65535,0"
xt "14250,57625,15000,58375"
)
tg (CPTG
uid 98,0
uid 796,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 99,0
uid 797,0
va (VaSet
font "Verdana,12,0"
)
@ -1207,28 +1210,28 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 100,0
uid 798,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7200,61000,8000"
st "testMode : IN std_uLogic ;"
st "testMode : IN std_uLogic ;
"
)
thePort (LogicalPort
lang 11
decl (Decl
n "testMode"
t "std_uLogic"
o 7
suid 10,0
suid 72,0
)
)
)
*86 (CptPort
uid 101,0
uid 799,0
ps "OnEdgeStrategy"
shape (Triangle
uid 102,0
uid 800,0
ro 90
va (VaSet
vasetType 1
@ -1237,11 +1240,11 @@ fg "0,65535,0"
xt "45000,7625,45750,8375"
)
tg (CPTG
uid 103,0
uid 801,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 104,0
uid 802,0
va (VaSet
font "Verdana,12,0"
)
@ -1253,30 +1256,30 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 105,0
uid 803,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10400,73500,11200"
st "testOut : OUT std_uLogic_vector (1 TO testLineNb) ;"
st "testOut : OUT std_uLogic_vector (1 TO testLineNb) ;
"
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 TO testLineNb)"
o 11
suid 11,0
suid 73,0
)
)
)
*87 (CptPort
uid 106,0
uid 804,0
ps "OnEdgeStrategy"
shape (Triangle
uid 107,0
uid 805,0
ro 270
va (VaSet
vasetType 1
@ -1285,11 +1288,11 @@ fg "0,65535,0"
xt "14250,45625,15000,46375"
)
tg (CPTG
uid 108,0
uid 806,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 109,0
uid 807,0
va (VaSet
font "Verdana,12,0"
)
@ -1300,12 +1303,13 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 110,0
uid 808,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11200,60000,12000"
st "unlock : OUT std_ulogic "
st "unlock : OUT std_ulogic
"
)
thePort (LogicalPort
lang 11
@ -1314,7 +1318,7 @@ decl (Decl
n "unlock"
t "std_ulogic"
o 12
suid 12,0
suid 74,0
)
)
)
@ -1403,7 +1407,7 @@ fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "36200,48000,45400,49000"
xt "36200,48000,46000,49000"
st "
by %user on %dd %month %year
"
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3910
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3402
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1513
Cursor/hds/when255/interface Normal file

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3400
Cursor/hds/when9/fsm.sm Normal file

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