mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-26 19:23:27 +00:00
5 lines
109 B
VHDL
5 lines
109 B
VHDL
ARCHITECTURE sim OF xor4 IS
|
|
BEGIN
|
|
xorOut <= in1 xor in2 xor in3 xor in4 after delay;
|
|
END ARCHITECTURE sim;
|