mirror of
https://github.com/Klagarge/Cursor.git
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2135 lines
26 KiB
Plaintext
2135 lines
26 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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|
suid 60,0
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|
usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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|
uid 137,0
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optionalChildren [
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|
*2 (RefLabelRowHdr
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|
)
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|
*3 (TitleRowHdr
|
|
)
|
|
*4 (FilterRowHdr
|
|
)
|
|
*5 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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|
)
|
|
*6 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
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|
)
|
|
*7 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
|
*8 (NameColHdr
|
|
tm "NameColHdrMgr"
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|
)
|
|
*9 (ModeColHdr
|
|
tm "ModeColHdrMgr"
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|
)
|
|
*10 (TypeColHdr
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|
tm "TypeColHdrMgr"
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|
)
|
|
*11 (BoundsColHdr
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|
tm "BoundsColHdrMgr"
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|
)
|
|
*12 (InitColHdr
|
|
tm "InitColHdrMgr"
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|
)
|
|
*13 (EolColHdr
|
|
tm "EolColHdrMgr"
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|
)
|
|
*14 (LogPort
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port (LogicalPort
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|
lang 11
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m 1
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|
decl (Decl
|
|
n "addressA"
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|
t "std_ulogic_vector"
|
|
b "(addressBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 49,0
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)
|
|
)
|
|
uid 646,0
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|
)
|
|
*15 (LogPort
|
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port (LogicalPort
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|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "addressB"
|
|
t "std_ulogic_vector"
|
|
b "(addressBitNb-1 DOWNTO 0)"
|
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o 2
|
|
suid 50,0
|
|
)
|
|
)
|
|
uid 648,0
|
|
)
|
|
*16 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clockA"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 51,0
|
|
)
|
|
)
|
|
uid 650,0
|
|
)
|
|
*17 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clockB"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 52,0
|
|
)
|
|
)
|
|
uid 652,0
|
|
)
|
|
*18 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "dataInA"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 53,0
|
|
)
|
|
)
|
|
uid 654,0
|
|
)
|
|
*19 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "dataInB"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 54,0
|
|
)
|
|
)
|
|
uid 656,0
|
|
)
|
|
*20 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "dataOutA"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
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posAdd 0
|
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o 7
|
|
suid 55,0
|
|
)
|
|
)
|
|
uid 658,0
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)
|
|
*21 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "dataOutB"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 56,0
|
|
)
|
|
)
|
|
uid 660,0
|
|
)
|
|
*22 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "enA"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 57,0
|
|
)
|
|
)
|
|
uid 662,0
|
|
)
|
|
*23 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "enB"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 58,0
|
|
)
|
|
)
|
|
uid 664,0
|
|
)
|
|
*24 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "writeEnA"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 59,0
|
|
)
|
|
)
|
|
uid 666,0
|
|
)
|
|
*25 (LogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "writeEnB"
|
|
t "std_ulogic"
|
|
o 12
|
|
suid 60,0
|
|
)
|
|
)
|
|
uid 668,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 150,0
|
|
optionalChildren [
|
|
*26 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
emptyMRCItem *27 (MRCItem
|
|
litem &1
|
|
pos 12
|
|
dimension 20
|
|
)
|
|
uid 152,0
|
|
optionalChildren [
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|
*28 (MRCItem
|
|
litem &2
|
|
pos 0
|
|
dimension 20
|
|
uid 153,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &3
|
|
pos 1
|
|
dimension 23
|
|
uid 154,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &4
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 155,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &14
|
|
pos 0
|
|
dimension 20
|
|
uid 647,0
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|
)
|
|
*32 (MRCItem
|
|
litem &15
|
|
pos 1
|
|
dimension 20
|
|
uid 649,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 20
|
|
uid 651,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 653,0
|
|
)
|
|
*35 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 20
|
|
uid 655,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 657,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 659,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 661,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &22
|
|
pos 8
|
|
dimension 20
|
|
uid 663,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &23
|
|
pos 9
|
|
dimension 20
|
|
uid 665,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &24
|
|
pos 10
|
|
dimension 20
|
|
uid 667,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &25
|
|
pos 11
|
|
dimension 20
|
|
uid 669,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
textAngle 90
|
|
)
|
|
uid 156,0
|
|
optionalChildren [
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|
*43 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 157,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 158,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 159,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 160,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 161,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 162,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 163,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 164,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 151,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 136,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *51 (LEmptyRow
|
|
)
|
|
uid 166,0
|
|
optionalChildren [
|
|
*52 (RefLabelRowHdr
|
|
)
|
|
*53 (TitleRowHdr
|
|
)
|
|
*54 (FilterRowHdr
|
|
)
|
|
*55 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*56 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*57 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*58 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*59 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*60 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*61 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*62 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*63 (LogGeneric
|
|
generic (GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 215,0
|
|
)
|
|
*64 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 217,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 178,0
|
|
optionalChildren [
|
|
*65 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *66 (MRCItem
|
|
litem &51
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 180,0
|
|
optionalChildren [
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|
*67 (MRCItem
|
|
litem &52
|
|
pos 0
|
|
dimension 20
|
|
uid 181,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &53
|
|
pos 1
|
|
dimension 23
|
|
uid 182,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &54
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 183,0
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|
)
|
|
*70 (MRCItem
|
|
litem &63
|
|
pos 0
|
|
dimension 20
|
|
uid 216,0
|
|
)
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|
*71 (MRCItem
|
|
litem &64
|
|
pos 1
|
|
dimension 20
|
|
uid 218,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
textAngle 90
|
|
)
|
|
uid 184,0
|
|
optionalChildren [
|
|
*72 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
uid 185,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &57
|
|
pos 1
|
|
dimension 50
|
|
uid 186,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &58
|
|
pos 2
|
|
dimension 100
|
|
uid 187,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &59
|
|
pos 3
|
|
dimension 100
|
|
uid 188,0
|
|
)
|
|
*76 (MRCItem
|
|
litem &60
|
|
pos 4
|
|
dimension 50
|
|
uid 189,0
|
|
)
|
|
*77 (MRCItem
|
|
litem &61
|
|
pos 5
|
|
dimension 50
|
|
uid 190,0
|
|
)
|
|
*78 (MRCItem
|
|
litem &62
|
|
pos 6
|
|
dimension 80
|
|
uid 191,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 179,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 165,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "bram_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "memory_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "bram_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/bram_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "bram_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
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