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103 lines
3.0 KiB
VHDL
103 lines
3.0 KiB
VHDL
LIBRARY BoardTester_test;
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USE BoardTester_test.testUtils.all;
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ARCHITECTURE test OF flash_tester IS
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constant T_W2: time := 0 ns;
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constant T_W3: time := 70 ns;
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constant T_W4: time := 50 ns;
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constant T_W5: time := 55 ns;
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constant T_W6: time := 10 ns;
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constant T_R3: time := 120 ns;
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signal addr: natural;
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signal data: integer;
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signal writeFlash: std_ulogic := '0';
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signal readFlash: std_ulogic := '0';
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constant separator : string(1 to 80) := (others => '-');
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constant indent : string(1 to 2) := (others => ' ');
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BEGIN
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------------------------------------------------------------------------------
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-- Test
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------------------------------------------------------------------------------
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process
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begin
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RP_n <= '1';
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wait for 1 us;
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print(cr & separator);
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-- erase block 0
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print(sprintf("%tu", now) & ": Erasing block 0");
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addr <= 16#10000#;
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data <= 16#20#;
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writeFlash <= '1', '0' after 1 ns;
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wait for 100 ns;
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data <= 16#D0#;
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writeFlash <= '1', '0' after 1 ns;
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wait for 2 us;
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-- program word
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print(sprintf("%tu", now) & ": Writing data into Flash");
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addr <= 16#0000#;
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data <= 16#0040#;
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writeFlash <= '1', '0' after 1 ns;
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wait for 100 ns;
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addr <= 16#0010#;
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data <= 16#CAFE#;
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writeFlash <= '1', '0' after 1 ns;
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wait for 2 us;
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-- read word
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print(sprintf("%tu", now) & ": Reading data from Flash");
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addr <= 16#0000#;
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readFlash <= '1', '0' after 1 ns;
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wait for 500 ns;
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-- read word
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print(sprintf("%tu", now) & ": Reading data from Flash");
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addr <= 16#0010#;
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readFlash <= '1', '0' after 1 ns;
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wait for 500 ns;
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wait;
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end process;
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------------------------------------------------------------------------------
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-- Board connections
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------------------------------------------------------------------------------
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CE(2 downto 1) <= (others => '0');
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BYTE_n <= '1';
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------------------------------------------------------------------------------
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-- Write access
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------------------------------------------------------------------------------
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process
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begin
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CE(0) <= '1';
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WE_N <= '1';
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OE_N <= '1';
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DQ <= (others => 'Z');
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wait on writeFlash, readFlash;
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if rising_edge(writeFlash) then
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A <= to_unsigned(addr, A'length) after T_W3 - T_W5;
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DQ <= std_logic_vector(to_unsigned(data, DQ'length)) after T_W3 - T_W4;
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CE(0) <= '0';
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wait for T_W2;
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WE_N <= '0';
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wait for T_W3;
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WE_N <= '1';
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wait for T_W6;
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-- CE(0) <= '1';
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elsif rising_edge(readFlash) then
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OE_N <= '0';
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A <= to_unsigned(addr, A'length);
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CE(0) <= '0';
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wait for T_R3 + 10 ns;
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-- CE(0) <= '1';
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end if;
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end process;
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END ARCHITECTURE test;
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