1
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mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-26 19:23:27 +00:00
Cursor/Cursor_test/hds/divider_tb/struct.bd
2021-11-24 10:50:51 +01:00

2771 lines
34 KiB
Plaintext

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
instances [
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name "I1"
duLibraryName "Cursor_test"
duName "divider_tester"
elements [
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mwi 0
uid 1774,0
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name "I0"
duLibraryName "Cursor"
duName "divider"
elements [
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mwi 0
uid 2524,0
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libraryRefs [
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
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variable " "
value " "
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variable "HDLDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.info"
)
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variable "SideDataUserDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd.user"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
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variable "appl"
value "HDL Designer"
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value "concatenated"
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variable "config"
value "%(unit)_%(view)_config"
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(vvPair
variable "d"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
)
(vvPair
variable "d_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb"
)
(vvPair
variable "date"
value "11.11.2019"
)
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variable "day"
value "Mon"
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variable "day_long"
value "Monday"
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(vvPair
variable "dd"
value "11"
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variable "entity_name"
value "divider_tb"
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(vvPair
variable "ext"
value "<TBD>"
)
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variable "f"
value "struct.bd"
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variable "f_logical"
value "struct.bd"
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(vvPair
variable "f_noext"
value "struct"
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variable "graphical_source_author"
value "silvan.zahno"
)
(vvPair
variable "graphical_source_date"
value "11.11.2019"
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(vvPair
variable "graphical_source_group"
value "UNKNOWN"
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(vvPair
variable "graphical_source_host"
value "WE6996"
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(vvPair
variable "graphical_source_time"
value "08:13:22"
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(vvPair
variable "group"
value "UNKNOWN"
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(vvPair
variable "host"
value "WE6996"
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(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Cursor_test"
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(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Cursor_test/work"
)
(vvPair
variable "mm"
value "11"
)
(vvPair
variable "module_name"
value "divider_tb"
)
(vvPair
variable "month"
value "Nov"
)
(vvPair
variable "month_long"
value "November"
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(vvPair
variable "p"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
)
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variable "p_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\divider_tb\\struct.bd"
)
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variable "package_name"
value "<Undefined Variable>"
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(vvPair
variable "project_name"
value "hds"
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(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
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variable "task_LeonardoPath"
value "<TBD>"
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variable "task_ModelSimPath"
value "C:\\EDA\\Modelsim\\win32"
)
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variable "task_NC"
value "<TBD>"
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variable "task_PrecisionRTLPath"
value "<TBD>"
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variable "task_QuestaSimPath"
value "<TBD>"
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variable "task_VCSPath"
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variable "this_ext"
value "bd"
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variable "this_file"
value "struct"
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(vvPair
variable "this_file_logical"
value "struct"
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(vvPair
variable "time"
value "08:13:22"
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(vvPair
variable "unit"
value "divider_tb"
)
(vvPair
variable "user"
value "silvan.zahno"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
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)
*71 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*72 (GroupColHdr
tm "GroupColHdrMgr"
)
*73 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*74 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*75 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*76 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*77 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*78 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*79 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 1,0
)
)
uid 2369,0
)
*80 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 2,0
)
)
uid 2371,0
)
*81 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "testMode"
t "std_uLogic"
o 5
suid 3,0
)
)
uid 2373,0
)
*82 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enPWM"
t "std_uLogic"
o 2
suid 6,0
)
)
uid 2379,0
)
*83 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enRamp"
t "std_uLogic"
o 3
suid 9,0
)
)
uid 2541,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 2395,0
optionalChildren [
*84 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *85 (MRCItem
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pos 5
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)
uid 2397,0
optionalChildren [
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pos 2
hidden 1
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pos 0
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pos 1
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pos 2
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pos 3
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uid 2380,0
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*93 (MRCItem
litem &83
pos 4
dimension 20
uid 2542,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 2401,0
optionalChildren [
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pos 0
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uid 2402,0
)
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uid 2404,0
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litem &75
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uid 2406,0
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litem &76
pos 5
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uid 2407,0
)
*100 (MRCItem
litem &77
pos 6
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uid 2408,0
)
*101 (MRCItem
litem &78
pos 7
dimension 80
uid 2409,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 2396,0
vaOverrides [
]
)
]
)
uid 2381,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *102 (LEmptyRow
)
uid 2411,0
optionalChildren [
*103 (RefLabelRowHdr
)
*104 (TitleRowHdr
)
*105 (FilterRowHdr
)
*106 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*107 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*108 (GroupColHdr
tm "GroupColHdrMgr"
)
*109 (NameColHdr
tm "GenericNameColHdrMgr"
)
*110 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*111 (InitColHdr
tm "GenericValueColHdrMgr"
)
*112 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*113 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 2423,0
optionalChildren [
*114 (Sheet
sheetRow (SheetRow
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cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
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pos 0
dimension 20
)
uid 2425,0
optionalChildren [
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pos 1
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*118 (MRCItem
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pos 2
hidden 1
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uid 2428,0
)
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)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
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uid 2429,0
optionalChildren [
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*120 (MRCItem
litem &108
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uid 2431,0
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*121 (MRCItem
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*122 (MRCItem
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dimension 100
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uid 2434,0
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*125 (MRCItem
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pos 6
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uid 2436,0
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)
fixedCol 3
fixedRow 2
name "Ports"
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vaOverrides [
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)
uid 2410,0
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)
activeModelName "BlockDiag"
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