mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
1231 lines
16 KiB
Plaintext
1231 lines
16 KiB
Plaintext
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version 2
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dialect 11
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tm "GenericPragmaColHdrMgr"
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*38 (EolColHdr
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tm "GenericEolColHdrMgr"
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pdm (PhysicalDM
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uid 111,0
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sheetRow (SheetRow
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headerVa (MVa
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cellVa (MVa
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cellColor "65535,65535,65535"
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groupVa (MVa
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litem &27
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dimension 20
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uid 82,0
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litem &28
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litem &33
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litem &37
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pos 5
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dimension 50
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*50 (MRCItem
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pos 6
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fixedCol 3
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uid 109,0
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type 1
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
|
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
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)
|
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(vvPair
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variable "HDSDir"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\symbol.sb.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\symbol.sb.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
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)
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(vvPair
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variable "appl"
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value "HDL Designer"
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variable "arch_name"
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value "symbol"
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(vvPair
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variable "concat_file"
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value "concatenated"
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
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)
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(vvPair
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variable "d_logical"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
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)
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(vvPair
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variable "date"
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value "17.12.2021"
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variable "day"
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value "ven."
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)
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(vvPair
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variable "day_long"
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value "vendredi"
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)
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(vvPair
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variable "dd"
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value "17"
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)
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(vvPair
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variable "entity_name"
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value "cursor_tb"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "symbol.sb"
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)
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(vvPair
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variable "f_logical"
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value "symbol.sb"
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)
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(vvPair
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variable "f_noext"
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value "symbol"
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)
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(vvPair
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variable "graphical_source_author"
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value "Simon"
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)
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(vvPair
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variable "graphical_source_date"
|
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value "17.12.2021"
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)
|
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(vvPair
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variable "graphical_source_group"
|
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value "UNKNOWN"
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(vvPair
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variable "graphical_source_host"
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value "PC-SDM"
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(vvPair
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variable "graphical_source_time"
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value "09:37:57"
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)
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(vvPair
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variable "group"
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value "UNKNOWN"
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)
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(vvPair
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variable "host"
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value "PC-SDM"
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)
|
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(vvPair
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variable "language"
|
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value "VHDL"
|
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)
|
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(vvPair
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variable "library"
|
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value "Cursor_test"
|
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)
|
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(vvPair
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variable "library_downstream_ModelSim"
|
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value "D:\\Users\\SysLo\\Master\\VHDL_comp"
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)
|
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(vvPair
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variable "library_downstream_ModelSimCompiler"
|
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value "$SCRATCH_DIR/Cursor_test/work"
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)
|
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(vvPair
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variable "mm"
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value "12"
|
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)
|
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(vvPair
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variable "module_name"
|
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value "cursor_tb"
|
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)
|
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(vvPair
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variable "month"
|
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value "d<>c."
|
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)
|
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(vvPair
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variable "month_long"
|
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value "d<>cembre"
|
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)
|
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(vvPair
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variable "p"
|
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\symbol.sb"
|
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)
|
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(vvPair
|
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variable "p_logical"
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value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\symbol.sb"
|
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)
|
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(vvPair
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variable "package_name"
|
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value "<Undefined Variable>"
|
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)
|
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(vvPair
|
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variable "project_name"
|
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value "hds"
|
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)
|
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(vvPair
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variable "series"
|
||
value "HDL Designer Series"
|
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)
|
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(vvPair
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variable "this_ext"
|
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value "sb"
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|
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variable "this_file"
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value "symbol"
|
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|
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(vvPair
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variable "this_file_logical"
|
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value "symbol"
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)
|
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(vvPair
|
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variable "time"
|
||
value "09:37:57"
|
||
)
|
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(vvPair
|
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variable "unit"
|
||
value "cursor_tb"
|
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)
|
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(vvPair
|
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variable "user"
|
||
value "Simon"
|
||
)
|
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(vvPair
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variable "version"
|
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value "2019.2 (Build 5)"
|
||
)
|
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(vvPair
|
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variable "view"
|
||
value "symbol"
|
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)
|
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(vvPair
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variable "year"
|
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value "2021"
|
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)
|
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(vvPair
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variable "yy"
|
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value "21"
|
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LanguageMgr "Vhdl2008LangMgr"
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uid 51,0
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optionalChildren [
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uid 8,0
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shape (Rectangle
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uid 9,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "29000,13000,56000,27000"
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oxt "15000,6000,20000,26000"
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biTextGroup (BiTextGroup
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uid 10,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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uid 11,0
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xt "29950,21900,37350,23100"
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blo "29950,22900"
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gi *52 (GenericInterface
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uid 13,0
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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xt "32000,27600,43500,28400"
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st "Generic Declarations"
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header "Generic Declarations"
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showHdrWhenContentsEmpty 1
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elements [
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]
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portInstanceVis (PortSigDisplay
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disp 1
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sT 1
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sIVOD 1
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*53 (Grouping
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uid 16,0
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uid 18,0
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text (MLText
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st "
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<enter project name here>
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tm "CommentText"
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wrapOption 3
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visibleHeight 1600
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visibleWidth 18600
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va (VaSet
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