mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-26 19:23:27 +00:00
19 lines
343 B
VHDL
19 lines
343 B
VHDL
ARCHITECTURE RTL OF counter IS
|
|
|
|
signal count: unsigned(countOut'range);
|
|
|
|
BEGIN
|
|
|
|
countEndlessly: process(reset, clock)
|
|
begin
|
|
if reset = '1' then
|
|
count <= (others => '0');
|
|
elsif rising_edge(clock) then
|
|
count <= count+1;
|
|
end if;
|
|
end process countEndlessly;
|
|
|
|
countOut <= count after delay;
|
|
|
|
END ARCHITECTURE RTL;
|