Cursor/Prefs/hds_user-linux/v2015.2/hds_user_prefs

version "45.1"
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win32DefaultEditor "Builtin"
win32DefaultViewer "Builtin"
unixDefaultEditor "Builtin"
unixDefaultViewer "Builtin"
defaultLanguage 0
defaultVerilogDialect 5
verilogSearchPath ""
syscUserIncPath ""
cppIncPath ""
printerCmdString "lp -c"
tabWidth 3
vhdlEntityExtension "vhd"
vhdlArchitectureExtensions [
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"vhdl"
"vho"
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verilogArchitectureExtensions [
"v"
"vlg"
"verilog"
"vo"
"sv"
"svh"
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verilogDefaultSaveName "untitled"
vhdlDefaultSaveName "untitled"
toolbarVisibility [
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"FcWindow:FormatText"
"StdWindow:FormatText"
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seperateElseBegincheck 1
ASICDesigner 1
FPGADesigner 1
AlteraLibraries 1
XilinxLibraries 1
userDefinedSimulatorTasks [
]
userDefinedSynthesisTasks [
]
simulator "ModelSim 5.1"
tempDirectory "/tmp"
projectPaths [
"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp"
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]
libMappingsRootDir ""
teamLibMappingsRootDir ""
defaultUserLibRootDir ""
projectSetupRootDir ""
defaultPackages "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
"
defaultVerilogPackages ""
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tableFont "courier,10,0"
pageSetupInfo (PageSetupInfo
toPrinter 1
exportedDirectories [
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exportStdIncludeRefs 1
exportStdPackageRefs 1
)
pageSizes [
]
exportPageSetupInfo (PageSetupInfo
ptrCmd "FrameMaker MIF"
toPrinter 1
exportedDirectories [
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]
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
exportHTMLPageSetupInfo (PageSetupInfo
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exportStdIncludeRefs 1
exportStdPackageRefs 1
)
exportHTMLPrintHierInfo (PrintHierInfo
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fg "49152,49152,49152"
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pageConnTextVaSet (VaSet
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teamPrefsPath ""
remoteSimPath "$HDS_TEAM_VER/remote"
mwMVL4 1
mwVerilogUseSynthesisPragmas 0
mwVhdlUseBusSlicesChkBox 0
mwVerilogUseBusSlicesChkBox 0
vmCheckInDesc ""
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(pair
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second ""
)
(pair
first "task_LeonardoPath"
second ""
)
(pair
first "task_ModelSimPath"
second "/usr/opt/Modelsim/modeltech/bin"
)
(pair
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second ""
)
(pair
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second ""
)
(pair
first "task_QuestaSimPath"
second ""
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(pair
first "task_VCSPath"
second ""
)
]
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"USER:Altera MegaWizard"
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"USER:FPGA Technology Setup"
"USER:FPGA Library Compile"
"USER:Xilinx Synthesis Tool"
"USER:Xilinx Place and Route"
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"USER:Quartus II Synthesis"
"USER:Quartus Place and Route"
"USER:Quartus Programmer"
"USER:Actel Place and Route"
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"USER:QuestaSim Flow"
"USER:LeonardoSpectrum Flow"
"USER:Precision Synthesis Flow"
"USER:Xilinx Synthesis Tool Flow"
"USER:Xilinx Vivado Flow"
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"\"USER:Quartus Programmer\""
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"\"USER:Xilinx CORE Generator\""
"\"USER:Xilinx Import\""
"\"USER:Xilinx Place and Route\""
"\"USER:Xilinx Platform Studio\""
"\"USER:Xilinx Synthesis Tool Flow\""
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(TaskPref
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(TaskPref
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Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp"
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Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp"
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packageListFontVaSet (VaSet
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panelTextVaSet (VaSet
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clockNameVaSet (VaSet
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compStateBoxNameVaSet (VaSet
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cptVaSet (VaSet
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blockPortVaSet (VaSet
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blkFrameVaSet (VaSet
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frameTxtVaSet (VaSet
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