Cursor/Libs/Lcd_test/hds/lcd@controller_tester/interface

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
libraryRefs [
"ieee"
]
)
version "27.1"
appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 76,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 42,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
decl (Decl
n "A0"
t "std_ulogic"
o 1
suid 67,0
)
)
uid 822,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ascii"
t "std_ulogic_vector"
b "(asciiBitNb-1 downto 0)"
o 6
suid 68,0
)
)
uid 824,0
)
*16 (LogPort
port (LogicalPort
decl (Decl
n "busy"
t "std_ulogic"
o 7
suid 69,0
)
)
uid 826,0
)
*17 (LogPort
port (LogicalPort
m 1
decl (Decl
n "clock"
t "std_ulogic"
o 8
suid 70,0
)
)
uid 828,0
)
*18 (LogPort
port (LogicalPort
decl (Decl
n "CS1_n"
t "std_ulogic"
o 2
suid 71,0
)
)
uid 830,0
)
*19 (LogPort
port (LogicalPort
m 1
decl (Decl
n "reset"
t "std_ulogic"
o 9
suid 72,0
)
)
uid 832,0
)
*20 (LogPort
port (LogicalPort
decl (Decl
n "RST_n"
t "std_ulogic"
o 3
suid 73,0
)
)
uid 834,0
)
*21 (LogPort
port (LogicalPort
decl (Decl
n "SCL"
t "std_ulogic"
o 4
suid 74,0
)
)
uid 836,0
)
*22 (LogPort
port (LogicalPort
m 1
decl (Decl
n "send"
t "std_ulogic"
o 10
suid 75,0
)
)
uid 838,0
)
*23 (LogPort
port (LogicalPort
decl (Decl
n "SI"
t "std_ulogic"
o 5
suid 76,0
)
)
uid 840,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 55,0
optionalChildren [
*24 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *25 (MRCItem
litem &1
pos 7
dimension 20
)
uid 57,0
optionalChildren [
*26 (MRCItem
litem &2
pos 0
dimension 20
uid 58,0
)
*27 (MRCItem
litem &3
pos 1
dimension 23
uid 59,0
)
*28 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 60,0
)
*29 (MRCItem
litem &14
pos 0
dimension 20
uid 823,0
)
*30 (MRCItem
litem &15
pos 1
dimension 20
uid 825,0
)
*31 (MRCItem
litem &16
pos 2
dimension 20
uid 827,0
)
*32 (MRCItem
litem &17
pos 3
dimension 20
uid 829,0
)
*33 (MRCItem
litem &18
pos 4
dimension 20
uid 831,0
)
*34 (MRCItem
litem &19
pos 5
dimension 20
uid 833,0
)
*35 (MRCItem
litem &20
pos 6
dimension 20
uid 835,0
)
*36 (MRCItem
litem &21
pos 7
dimension 20
uid 837,0
)
*37 (MRCItem
litem &22
pos 8
dimension 20
uid 839,0
)
*38 (MRCItem
litem &23
pos 9
dimension 20
uid 841,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 61,0
optionalChildren [
*39 (MRCItem
litem &5
pos 0
dimension 20
uid 62,0
)
*40 (MRCItem
litem &7
pos 1
dimension 50
uid 63,0
)
*41 (MRCItem
litem &8
pos 2
dimension 100
uid 64,0
)
*42 (MRCItem
litem &9
pos 3
dimension 50
uid 65,0
)
*43 (MRCItem
litem &10
pos 4
dimension 100
uid 66,0
)
*44 (MRCItem
litem &11
pos 5
dimension 100
uid 67,0
)
*45 (MRCItem
litem &12
pos 6
dimension 50
uid 68,0
)
*46 (MRCItem
litem &13
pos 7
dimension 80
uid 69,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 56,0
vaOverrides [
]
)
]
)
uid 41,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *47 (LEmptyRow
)
uid 71,0
optionalChildren [
*48 (RefLabelRowHdr
)
*49 (TitleRowHdr
)
*50 (FilterRowHdr
)
*51 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*52 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*53 (GroupColHdr
tm "GroupColHdrMgr"
)
*54 (NameColHdr
tm "GenericNameColHdrMgr"
)
*55 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*56 (InitColHdr
tm "GenericValueColHdrMgr"
)
*57 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*58 (EolColHdr
tm "GenericEolColHdrMgr"
)
*59 (LogGeneric
generic (GiElement
name "clockFrequency"
type "real"
value "100.0e6"
)
uid 120,0
)
*60 (LogGeneric
generic (GiElement
name "asciiBitNb"
type "positive"
value "7"
)
uid 375,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 83,0
optionalChildren [
*61 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *62 (MRCItem
litem &47
pos 2
dimension 20
)
uid 85,0
optionalChildren [
*63 (MRCItem
litem &48
pos 0
dimension 20
uid 86,0
)
*64 (MRCItem
litem &49
pos 1
dimension 23
uid 87,0
)
*65 (MRCItem
litem &50
pos 2
hidden 1
dimension 20
uid 88,0
)
*66 (MRCItem
litem &59
pos 0
dimension 20
uid 121,0
)
*67 (MRCItem
litem &60
pos 1
dimension 20
uid 376,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 89,0
optionalChildren [
*68 (MRCItem
litem &51
pos 0
dimension 20
uid 90,0
)
*69 (MRCItem
litem &53
pos 1
dimension 50
uid 91,0
)
*70 (MRCItem
litem &54
pos 2
dimension 100
uid 92,0
)
*71 (MRCItem
litem &55
pos 3
dimension 100
uid 93,0
)
*72 (MRCItem
litem &56
pos 4
dimension 50
uid 94,0
)
*73 (MRCItem
litem &57
pos 5
dimension 50
uid 95,0
)
*74 (MRCItem
litem &58
pos 6
dimension 80
uid 96,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 84,0
vaOverrides [
]
)
]
)
uid 70,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tester"
)
(vvPair
variable "d_logical"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tester"
)
(vvPair
variable "date"
value "11.11.2019"
)
(vvPair
variable "day"
value "Mon"
)
(vvPair
variable "day_long"
value "Monday"
)
(vvPair
variable "dd"
value "11"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "lcdController_tester"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "f_noext"
value "interface"
)
(vvPair
variable "graphical_source_author"
value "silvan.zahno"
)
(vvPair
variable "graphical_source_date"
value "11.11.2019"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE6996"
)
(vvPair
variable "graphical_source_time"
value "07:37:47"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE6996"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Lcd_test"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/ElN/Libraries/Lcd_test/work"
)
(vvPair
variable "mm"
value "11"
)
(vvPair
variable "module_name"
value "lcdController_tester"
)
(vvPair
variable "month"
value "Nov"
)
(vvPair
variable "month_long"
value "November"
)
(vvPair
variable "p"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcd@controller_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Lcd_test\\hds\\lcdController_tester\\interface"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$SCRATCH_DIR\\BoardTester\\Board\\ise"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "<TBD>"
)
(vvPair
variable "this_file"
value "interface"
)
(vvPair
variable "this_file_logical"
value "interface"
)
(vvPair
variable "time"
value "07:37:47"
)
(vvPair
variable "unit"
value "lcdController_tester"
)
(vvPair
variable "user"
value "silvan.zahno"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 40,0
optionalChildren [
*75 (SymbolBody
uid 8,0
optionalChildren [
*76 (CptPort
uid 772,0
ps "OnEdgeStrategy"
shape (Triangle
uid 773,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58625,5250,59375,6000"
)
tg (CPTG
uid 774,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 775,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "58300,7000,59700,9400"
st "A0"
ju 2
blo "59500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 776,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,1800,59500,2600"
st "A0    : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "A0"
t "std_ulogic"
o 1
suid 67,0
)
)
)
*77 (CptPort
uid 777,0
ps "OnEdgeStrategy"
shape (Triangle
uid 778,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "22625,5250,23375,6000"
)
tg (CPTG
uid 779,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 780,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "22300,7000,23700,10500"
st "ascii"
ju 2
blo "23500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 781,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6600,75000,7400"
st "ascii : OUT    std_ulogic_vector (asciiBitNb-1 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ascii"
t "std_ulogic_vector"
b "(asciiBitNb-1 downto 0)"
o 6
suid 68,0
)
)
)
*78 (CptPort
uid 782,0
ps "OnEdgeStrategy"
shape (Triangle
uid 783,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26625,5250,27375,6000"
)
tg (CPTG
uid 784,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 785,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "26300,7000,27700,10800"
st "busy"
ju 2
blo "27500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 786,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5800,59500,6600"
st "busy  : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "busy"
t "std_ulogic"
o 7
suid 69,0
)
)
)
*79 (CptPort
uid 787,0
ps "OnEdgeStrategy"
shape (Triangle
uid 788,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "30625,5250,31375,6000"
)
tg (CPTG
uid 789,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 790,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "30300,7000,31700,10800"
st "clock"
ju 2
blo "31500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 791,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7400,59500,8200"
st "clock : OUT    std_ulogic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "clock"
t "std_ulogic"
o 8
suid 70,0
)
)
)
*80 (CptPort
uid 792,0
ps "OnEdgeStrategy"
shape (Triangle
uid 793,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "54625,5250,55375,6000"
)
tg (CPTG
uid 794,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 795,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "54300,7000,55700,11900"
st "CS1_n"
ju 2
blo "55500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 796,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2600,59500,3400"
st "CS1_n : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "CS1_n"
t "std_ulogic"
o 2
suid 71,0
)
)
)
*81 (CptPort
uid 797,0
ps "OnEdgeStrategy"
shape (Triangle
uid 798,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "32625,5250,33375,6000"
)
tg (CPTG
uid 799,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 800,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "32300,7000,33700,11100"
st "reset"
ju 2
blo "33500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 801,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8200,59500,9000"
st "reset : OUT    std_ulogic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "reset"
t "std_ulogic"
o 9
suid 72,0
)
)
)
*82 (CptPort
uid 802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 803,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "56625,5250,57375,6000"
)
tg (CPTG
uid 804,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 805,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "56300,7000,57700,11700"
st "RST_n"
ju 2
blo "57500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 806,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3400,59500,4200"
st "RST_n : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "RST_n"
t "std_ulogic"
o 3
suid 73,0
)
)
)
*83 (CptPort
uid 807,0
ps "OnEdgeStrategy"
shape (Triangle
uid 808,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60625,5250,61375,6000"
)
tg (CPTG
uid 809,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 810,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "60300,7000,61700,10200"
st "SCL"
ju 2
blo "61500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 811,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4200,59500,5000"
st "SCL   : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SCL"
t "std_ulogic"
o 4
suid 74,0
)
)
)
*84 (CptPort
uid 812,0
ps "OnEdgeStrategy"
shape (Triangle
uid 813,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24625,5250,25375,6000"
)
tg (CPTG
uid 814,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 815,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "24300,7000,25700,10900"
st "send"
ju 2
blo "25500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 816,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9000,58500,9800"
st "send  : OUT    std_ulogic 
"
)
thePort (LogicalPort
m 1
decl (Decl
n "send"
t "std_ulogic"
o 10
suid 75,0
)
)
)
*85 (CptPort
uid 817,0
ps "OnEdgeStrategy"
shape (Triangle
uid 818,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62625,5250,63375,6000"
)
tg (CPTG
uid 819,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 820,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "62300,7000,63700,9100"
st "SI"
ju 2
blo "63500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 821,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5000,59500,5800"
st "SI    : IN     std_ulogic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SI"
t "std_ulogic"
o 5
suid 76,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,71000,14000"
)
oxt "15000,6000,75000,14000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Verdana,9,1"
)
xt "37100,8800,42100,10000"
st "Lcd_test"
blo "37100,9800"
)
second (Text
uid 12,0
va (VaSet
font "Verdana,9,1"
)
xt "37100,10000,48900,11200"
st "lcdController_tester"
blo "37100,11000"
)
)
gi *86 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Verdana,8,0"
)
xt "20000,6000,34900,10000"
st "Generic Declarations

clockFrequency real     100.0e6  
asciiBitNb     positive 7        "
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "clockFrequency"
type "real"
value "100.0e6"
)
(GiElement
name "asciiBitNb"
type "positive"
value "7"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *87 (PackageList
uid 16,0
stg "VerticalLayoutStrategy"
textVec [
*88 (Text
uid 17,0
va (VaSet
font "Verdana,9,1"
)
xt "0,0,6500,900"
st "Package List"
blo "0,700"
)
*89 (MLText
uid 18,0
va (VaSet
)
xt "0,1200,17500,4800"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
windowSize "141,44,1158,734"
viewArea "-500,-500,71320,48820"
cachedDiagramExtent "0,0,67000,14000"
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName "Lcd_test"
entityName "lcdController_tb"
viewName "struct.bd"
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,31000,26000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "Verdana,9,1"
)
xt "20300,14800,25700,16000"
st "<library>"
blo "20300,15800"
)
second (Text
va (VaSet
font "Verdana,9,1"
)
xt "20300,16000,24200,17200"
st "<cell>"
blo "20300,17000"
)
)
gi *90 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Verdana,8,0"
)
xt "0,12000,9700,13000"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sIVOD 1
)
portVis (PortSigDisplay
sTC 0
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2500,1950"
st "In0"
blo "0,1750"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Verdana,8,0"
)
)
thePort (LogicalPort
decl (Decl
n "In0"
t "std_ulogic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,4300,1950"
st "Buffer0"
blo "0,1750"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Verdana,8,0"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Buffer0"
t "std_ulogic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *91 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,9,1"
)
xt "42000,0,48500,900"
st "Declarations"
blo "42000,700"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,9,1"
)
xt "42000,900,45000,1800"
st "Ports:"
blo "42000,1600"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Verdana,9,1"
)
xt "42000,9800,44500,10700"
st "User:"
blo "42000,10500"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "42000,0,49500,900"
st "Internal User:"
blo "42000,700"
)
externalText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "44000,10700,44000,10700"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 841,0
activeModelName "Symbol:GEN"
)