mirror of
https://github.com/Klagarge/Cursor.git
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1450 lines
18 KiB
Plaintext
1450 lines
18 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
|
|
commonDM (CommonDM
|
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ldm (LogicalDM
|
|
suid 2002,0
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|
usingSuid 1
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|
emptyRow *1 (LEmptyRow
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|
)
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|
uid 99,0
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|
optionalChildren [
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|
*2 (LogPort
|
|
port (LogicalPort
|
|
m 1
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|
decl (Decl
|
|
n "out1"
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t "std_uLogic"
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|
o 2
|
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suid 2,0
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)
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)
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|
uid 100,0
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|
)
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|
*3 (LogPort
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port (LogicalPort
|
|
decl (Decl
|
|
n "in1"
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|
t "std_uLogic"
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|
o 1
|
|
suid 1,0
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)
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)
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|
uid 101,0
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|
)
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|
*4 (RefLabelRowHdr
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|
)
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|
*5 (TitleRowHdr
|
|
)
|
|
*6 (FilterRowHdr
|
|
)
|
|
*7 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*8 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*9 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*10 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*11 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*12 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*13 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*14 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*15 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 102,0
|
|
optionalChildren [
|
|
*16 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
)
|
|
emptyMRCItem *17 (MRCItem
|
|
litem &1
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 43,0
|
|
optionalChildren [
|
|
*18 (MRCItem
|
|
litem &4
|
|
pos 0
|
|
dimension 20
|
|
uid 46,0
|
|
)
|
|
*19 (MRCItem
|
|
litem &5
|
|
pos 1
|
|
dimension 23
|
|
uid 48,0
|
|
)
|
|
*20 (MRCItem
|
|
litem &6
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 50,0
|
|
)
|
|
*21 (MRCItem
|
|
litem &2
|
|
pos 1
|
|
dimension 20
|
|
uid 69,0
|
|
)
|
|
*22 (MRCItem
|
|
litem &3
|
|
pos 0
|
|
dimension 20
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|
uid 70,0
|
|
)
|
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]
|
|
)
|
|
sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
|
|
textAngle 90
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)
|
|
uid 44,0
|
|
optionalChildren [
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|
*23 (MRCItem
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litem &7
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pos 0
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dimension 20
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uid 52,0
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)
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*24 (MRCItem
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litem &9
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pos 1
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dimension 50
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uid 56,0
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)
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*25 (MRCItem
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|
litem &10
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pos 2
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dimension 100
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uid 58,0
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)
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|
*26 (MRCItem
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litem &11
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pos 3
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dimension 50
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uid 60,0
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|
)
|
|
*27 (MRCItem
|
|
litem &12
|
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pos 4
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dimension 100
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|
uid 62,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &13
|
|
pos 5
|
|
dimension 100
|
|
uid 64,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &14
|
|
pos 6
|
|
dimension 50
|
|
uid 66,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &15
|
|
pos 7
|
|
dimension 80
|
|
uid 68,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 42,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 98,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *31 (LEmptyRow
|
|
)
|
|
uid 104,0
|
|
optionalChildren [
|
|
*32 (RefLabelRowHdr
|
|
)
|
|
*33 (TitleRowHdr
|
|
)
|
|
*34 (FilterRowHdr
|
|
)
|
|
*35 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*36 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*37 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*38 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*39 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*40 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*41 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*42 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*43 (LogGeneric
|
|
generic (GiElement
|
|
name "delay"
|
|
type "time"
|
|
value "gateDelay"
|
|
)
|
|
uid 96,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 105,0
|
|
optionalChildren [
|
|
*44 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *45 (MRCItem
|
|
litem &31
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 72,0
|
|
optionalChildren [
|
|
*46 (MRCItem
|
|
litem &32
|
|
pos 0
|
|
dimension 20
|
|
uid 75,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &33
|
|
pos 1
|
|
dimension 23
|
|
uid 77,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &34
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 79,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &43
|
|
pos 0
|
|
dimension 20
|
|
uid 97,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 73,0
|
|
optionalChildren [
|
|
*50 (MRCItem
|
|
litem &35
|
|
pos 0
|
|
dimension 20
|
|
uid 81,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &37
|
|
pos 1
|
|
dimension 50
|
|
uid 85,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &38
|
|
pos 2
|
|
dimension 100
|
|
uid 87,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &39
|
|
pos 3
|
|
dimension 100
|
|
uid 89,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &40
|
|
pos 4
|
|
dimension 50
|
|
uid 91,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &41
|
|
pos 5
|
|
dimension 50
|
|
uid 93,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &42
|
|
pos 6
|
|
dimension 80
|
|
uid 95,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 71,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 103,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:35:14"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "gates"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Sep"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "September"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\inverter\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelPath"
|
|
value "$ACTEL_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ActelProjectPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:35:14"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 29,0
|
|
optionalChildren [
|
|
*57 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*58 (CptPort
|
|
uid 16,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 17,0
|
|
ro 90
|
|
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|
xt "26910,25700,29510,26700"
|
|
st "<cell>"
|
|
blo "26910,26500"
|
|
)
|
|
)
|
|
gi *76 (GenericInterface
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,5000,20000,5000"
|
|
)
|
|
header "Generic Declarations"
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portInstanceVis (PortSigDisplay
|
|
sT 1
|
|
sIVOD 1
|
|
)
|
|
portVis (PortSigDisplay
|
|
sIVOD 1
|
|
)
|
|
)
|
|
defaultCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,1500,1650"
|
|
st "In0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "In0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
bg "0,0,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,3500,1650"
|
|
st "Buffer0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *77 (SymDeclBlock
|
|
uid 31,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7800,5400,8800"
|
|
st "Declarations"
|
|
blo "0,8600"
|
|
)
|
|
portLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,8800,2700,9800"
|
|
st "Ports:"
|
|
blo "0,9600"
|
|
)
|
|
externalLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,11600,2500,12500"
|
|
st "User:"
|
|
blo "0,12300"
|
|
)
|
|
internalLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,15900,5800,16900"
|
|
st "Internal User:"
|
|
blo "0,16700"
|
|
)
|
|
externalText (MLText
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,12500,2000,12500"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 4,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,17600,2000,17600"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 298,0
|
|
activeModelName "Symbol"
|
|
)
|