mirror of
https://github.com/Klagarge/Cursor.git
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1338 lines
17 KiB
Plaintext
1338 lines
17 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2002,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 99,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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n "logic_1"
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t "std_uLogic"
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o 1
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suid 2,0
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)
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)
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uid 100,0
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)
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*3 (RefLabelRowHdr
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)
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*4 (TitleRowHdr
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)
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|
*5 (FilterRowHdr
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)
|
|
*6 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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|
)
|
|
*7 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
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|
)
|
|
*8 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
|
*9 (NameColHdr
|
|
tm "NameColHdrMgr"
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|
)
|
|
*10 (ModeColHdr
|
|
tm "ModeColHdrMgr"
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|
)
|
|
*11 (TypeColHdr
|
|
tm "TypeColHdrMgr"
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|
)
|
|
*12 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
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|
)
|
|
*13 (InitColHdr
|
|
tm "InitColHdrMgr"
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|
)
|
|
*14 (EolColHdr
|
|
tm "EolColHdrMgr"
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|
)
|
|
]
|
|
)
|
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pdm (PhysicalDM
|
|
uid 102,0
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|
optionalChildren [
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*15 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
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emptyMRCItem *16 (MRCItem
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litem &1
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|
pos 1
|
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dimension 20
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)
|
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uid 43,0
|
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optionalChildren [
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*17 (MRCItem
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litem &3
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pos 0
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dimension 20
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uid 46,0
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)
|
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*18 (MRCItem
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litem &4
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pos 1
|
|
dimension 23
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|
uid 48,0
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|
)
|
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*19 (MRCItem
|
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litem &5
|
|
pos 2
|
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hidden 1
|
|
dimension 20
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uid 50,0
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)
|
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*20 (MRCItem
|
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litem &2
|
|
pos 0
|
|
dimension 20
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|
uid 69,0
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|
)
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]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
textAngle 90
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)
|
|
uid 44,0
|
|
optionalChildren [
|
|
*21 (MRCItem
|
|
litem &6
|
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pos 0
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dimension 20
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uid 52,0
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)
|
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*22 (MRCItem
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litem &8
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pos 1
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dimension 50
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uid 56,0
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)
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*23 (MRCItem
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litem &9
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pos 2
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dimension 100
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uid 58,0
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)
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*24 (MRCItem
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litem &10
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pos 3
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dimension 50
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uid 60,0
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)
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*25 (MRCItem
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litem &11
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pos 4
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dimension 100
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uid 62,0
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)
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*26 (MRCItem
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litem &12
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pos 5
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dimension 100
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uid 64,0
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)
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*27 (MRCItem
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litem &13
|
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pos 6
|
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dimension 50
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|
uid 66,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &14
|
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pos 7
|
|
dimension 80
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|
uid 68,0
|
|
)
|
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]
|
|
)
|
|
fixedCol 4
|
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fixedRow 2
|
|
name "Ports"
|
|
uid 42,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 98,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *29 (LEmptyRow
|
|
)
|
|
uid 104,0
|
|
optionalChildren [
|
|
*30 (RefLabelRowHdr
|
|
)
|
|
*31 (TitleRowHdr
|
|
)
|
|
*32 (FilterRowHdr
|
|
)
|
|
*33 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*34 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*35 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*36 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*37 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*38 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*39 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*40 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 105,0
|
|
optionalChildren [
|
|
*41 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *42 (MRCItem
|
|
litem &29
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 72,0
|
|
optionalChildren [
|
|
*43 (MRCItem
|
|
litem &30
|
|
pos 0
|
|
dimension 20
|
|
uid 75,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &31
|
|
pos 1
|
|
dimension 23
|
|
uid 77,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &32
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 79,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 73,0
|
|
optionalChildren [
|
|
*46 (MRCItem
|
|
litem &33
|
|
pos 0
|
|
dimension 20
|
|
uid 81,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &35
|
|
pos 1
|
|
dimension 50
|
|
uid 85,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &36
|
|
pos 2
|
|
dimension 100
|
|
uid 87,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &37
|
|
pos 3
|
|
dimension 100
|
|
uid 89,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &38
|
|
pos 4
|
|
dimension 50
|
|
uid 91,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &39
|
|
pos 5
|
|
dimension 50
|
|
uid 93,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &40
|
|
pos 6
|
|
dimension 80
|
|
uid 95,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 71,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 103,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "logic1"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:35:13"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "gates"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "logic1"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Sep"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "September"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\logic1\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Projects\\Levisat\\Onboard\\FPGA\\board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "c:\\eda\\modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:35:13"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "logic1"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 29,0
|
|
optionalChildren [
|
|
*53 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*54 (CptPort
|
|
uid 22,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 23,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36625,21000,37375,21750"
|
|
)
|
|
tg (CPTG
|
|
uid 39,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 25,0
|
|
va (VaSet
|
|
)
|
|
xt "38000,20000,40900,21000"
|
|
st "logic_1"
|
|
blo "38000,20800"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 35,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,9800,14700,10800"
|
|
st "logic_1 : OUT std_uLogic "
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "logic_1"
|
|
t "std_uLogic"
|
|
o 1
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Pu
|
|
uid 279,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
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