mirror of
https://github.com/Klagarge/Cursor.git
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1502 lines
19 KiB
Plaintext
1502 lines
19 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
|
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commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 2003,0
|
|
usingSuid 1
|
|
emptyRow *1 (LEmptyRow
|
|
)
|
|
uid 148,0
|
|
optionalChildren [
|
|
*2 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in1"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 149,0
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|
)
|
|
*3 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in2"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 150,0
|
|
)
|
|
*4 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "xorOut"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 151,0
|
|
)
|
|
*5 (RefLabelRowHdr
|
|
)
|
|
*6 (TitleRowHdr
|
|
)
|
|
*7 (FilterRowHdr
|
|
)
|
|
*8 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*9 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*10 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*11 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*12 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*13 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*14 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*15 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*16 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 152,0
|
|
optionalChildren [
|
|
*17 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *18 (MRCItem
|
|
litem &1
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 91,0
|
|
optionalChildren [
|
|
*19 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 94,0
|
|
)
|
|
*20 (MRCItem
|
|
litem &6
|
|
pos 1
|
|
dimension 23
|
|
uid 96,0
|
|
)
|
|
*21 (MRCItem
|
|
litem &7
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 98,0
|
|
)
|
|
*22 (MRCItem
|
|
litem &2
|
|
pos 0
|
|
dimension 20
|
|
uid 117,0
|
|
)
|
|
*23 (MRCItem
|
|
litem &3
|
|
pos 1
|
|
dimension 20
|
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uid 118,0
|
|
)
|
|
*24 (MRCItem
|
|
litem &4
|
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pos 2
|
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dimension 20
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uid 119,0
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)
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]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
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font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 92,0
|
|
optionalChildren [
|
|
*25 (MRCItem
|
|
litem &8
|
|
pos 0
|
|
dimension 20
|
|
uid 100,0
|
|
)
|
|
*26 (MRCItem
|
|
litem &10
|
|
pos 1
|
|
dimension 50
|
|
uid 104,0
|
|
)
|
|
*27 (MRCItem
|
|
litem &11
|
|
pos 2
|
|
dimension 100
|
|
uid 106,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &12
|
|
pos 3
|
|
dimension 50
|
|
uid 108,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &13
|
|
pos 4
|
|
dimension 100
|
|
uid 110,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &14
|
|
pos 5
|
|
dimension 100
|
|
uid 112,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &15
|
|
pos 6
|
|
dimension 50
|
|
uid 114,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &16
|
|
pos 7
|
|
dimension 80
|
|
uid 116,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 90,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 147,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *33 (LEmptyRow
|
|
)
|
|
uid 154,0
|
|
optionalChildren [
|
|
*34 (RefLabelRowHdr
|
|
)
|
|
*35 (TitleRowHdr
|
|
)
|
|
*36 (FilterRowHdr
|
|
)
|
|
*37 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*38 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*39 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*40 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*41 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*42 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*43 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*44 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*45 (LogGeneric
|
|
generic (GiElement
|
|
name "delay"
|
|
type "time"
|
|
value "gateDelay"
|
|
)
|
|
uid 145,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 155,0
|
|
optionalChildren [
|
|
*46 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *47 (MRCItem
|
|
litem &33
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 121,0
|
|
optionalChildren [
|
|
*48 (MRCItem
|
|
litem &34
|
|
pos 0
|
|
dimension 20
|
|
uid 124,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &35
|
|
pos 1
|
|
dimension 23
|
|
uid 126,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &36
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 128,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &45
|
|
pos 0
|
|
dimension 20
|
|
uid 146,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 122,0
|
|
optionalChildren [
|
|
*52 (MRCItem
|
|
litem &37
|
|
pos 0
|
|
dimension 20
|
|
uid 130,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 50
|
|
uid 134,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &40
|
|
pos 2
|
|
dimension 100
|
|
uid 136,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &41
|
|
pos 3
|
|
dimension 100
|
|
uid 138,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &42
|
|
pos 4
|
|
dimension 50
|
|
uid 140,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &43
|
|
pos 5
|
|
dimension 50
|
|
uid 142,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &44
|
|
pos 6
|
|
dimension 80
|
|
uid 144,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 120,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 153,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "xor2"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:35:03"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "gates"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "xor2"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Sep"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "September"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\xor2\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\Board\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "c:\\eda\\modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:35:03"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "xor2"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 83,0
|
|
optionalChildren [
|
|
*59 (SymbolBody
|
|
uid 11,0
|
|
optionalChildren [
|
|
*60 (CptPort
|
|
uid 51,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 52,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42000,17625,42750,18375"
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|
fg "65535,65535,65535"
|
|
lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "1350,1100,4150,2100"
|
|
st "Panel0"
|
|
blo "1350,1900"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
parentGraphicsRef (HdmGraphicsRef
|
|
libraryName ""
|
|
entityName ""
|
|
viewName ""
|
|
)
|
|
defaultSymbolBody (SymbolBody
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "15000,16000,42000,36000"
|
|
)
|
|
biTextGroup (BiTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "26600,24700,30200,25700"
|
|
st "<library>"
|
|
blo "26600,25500"
|
|
)
|
|
second (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "26600,25700,29200,26700"
|
|
st "<cell>"
|
|
blo "26600,26500"
|
|
)
|
|
)
|
|
gi *78 (GenericInterface
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,5000,20000,5000"
|
|
)
|
|
header "Generic Declarations"
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portInstanceVis (PortSigDisplay
|
|
sT 1
|
|
sIVOD 1
|
|
)
|
|
portVis (PortSigDisplay
|
|
sIVOD 1
|
|
)
|
|
)
|
|
defaultCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,1500,1650"
|
|
st "In0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "In0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
bg "0,0,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,750,3500,1650"
|
|
st "Buffer0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *79 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7800,5400,8800"
|
|
st "Declarations"
|
|
blo "0,8600"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,8800,2700,9800"
|
|
st "Ports:"
|
|
blo "0,9600"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,12500,2500,13400"
|
|
st "User:"
|
|
blo "0,13200"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7800,5800,8800"
|
|
st "Internal User:"
|
|
blo "0,8600"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,13400,2000,13400"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "18000,7800,18000,7800"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 325,0
|
|
activeModelName "Symbol"
|
|
)
|