mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-26 19:23:27 +00:00
6 lines
147 B
VHDL
6 lines
147 B
VHDL
ARCHITECTURE sim OF tristateBufferSigned IS
|
|
BEGIN
|
|
out1 <= in1 after delay when OE = '1' else (others => 'Z') after delay;
|
|
END ARCHITECTURE sim;
|
|
|