mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-26 19:23:27 +00:00
529 lines
21 KiB
VHDL
529 lines
21 KiB
VHDL
use std.textio.all;
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ARCHITECTURE behav OF flash_28F128J3A IS
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-- controls
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signal chipSelect : std_ulogic;
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signal writePulse : std_ulogic;
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signal writePulseDelayed : std_ulogic;
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signal memoryCommand : unsigned(7 downto 0);
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signal wordProgramBusy : std_ulogic := '0';
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signal blockEraseBusy : std_ulogic := '0';
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signal busy : std_ulogic;
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signal readPulseCs : std_ulogic := '0';
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signal readPulseOe : std_ulogic := '0';
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signal readPulse : std_ulogic;
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signal memoryAddressDebug : unsigned(A'range);
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type state_type is (
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READ_ARRAY,
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READ_ID_CODES,
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READ_QUERY,
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READ_STATUS,
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WRITE_BUFFER,
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WORD_PROGRAM_1,
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WORD_PROGRAM_2,
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BLOCK_ERASE_1,
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BLOCK_ERASE_2,
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CONFIG,
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PROG_LOCK_BITS,
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PROG_PROT,
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BOTCH_LOCK,--
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BOTCH_LOCK_ERS_SUSP,--
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LOCK_DONE,
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PROG_LOCK_BITS_ERS_SUSP,--
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LOCK_DONE_ERS_SUSP,
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PROT_PROG_BUSY,--
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PROT_PROG_DONE,--
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WORD_PROGRAM_1_ERS_SUSP,--
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PROG_BUSY,--
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PROG_BUSY_ERS_SUSP,--
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READ_STATUS_PROG_SUSP,--
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READ_ARRAY_PROG_SUSP,--
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READ_CONFIG_PROG_SUSP,--
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READ_QUERY_PROG_SUSP,--
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PROGRAM_DONE,--
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PROGRAM_DONE_ERS_SUSP,--
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BOTCH_ERS,--
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ERASE_BUSY,--
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READ_STATUS_ERS_SUSP,--
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READ_ARRAY_ERS_SUSP,--
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READ_CONFIG_ERS_SUSP,--
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READ_QUERY_ERS_SUSP,--
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ERASE_DONE--
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);
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signal currentState : state_type;
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signal nextState : state_type;
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-- storage
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constant blockLength : positive:= 16#10000#; -- 64 Kword blocks
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constant memoryLength: positive := 2**(A'length-1);
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-- constant memoryLength : positive := 2*blockLength;
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subtype memoryWord is std_ulogic_vector(DQ'range);
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type memoryArray is array(0 to memoryLength-1) of memoryWord;
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signal memoryDataWord : memoryWord;
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BEGIN
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--############################################################################
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-- Controls
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------------------------------------------------------------------------------
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chipSelect <= ( (not CE(2)) and (not CE(1)) and (not CE(0)) ) or
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( CE(2) and ( (not CE(1)) or (not CE(0)) ) );
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writePulse <= chipSelect and not(WE_n);
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writePulseDelayed <= writePulse after 1 ns;
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memoryCommand <= unsigned(DQ(memoryCommand'range));
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process(chipSelect)
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begin
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if rising_edge(chipSelect) then
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readPulseCs <= '1' after T_R3;
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elsif falling_edge(chipSelect) then
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readPulseCs <= '0' after T_R8;
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end if;
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end process;
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process(OE_n)
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begin
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if falling_edge(OE_n) then
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readPulseOe <= '1' after T_R7;
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elsif rising_edge(OE_n) then
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readPulseOe <= '0' after T_R9;
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end if;
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end process;
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readPulse <= readPulseCs and readPulseOe;
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------------------------------------------------------------------------------
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-- Programming delays
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------------------------------------------------------------------------------
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wordProgramBusy <= '1', '0' after T_W16_program when currentState = WORD_PROGRAM_2;
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blockEraseBusy <= '1', '0' after T_W16_erase when currentState = BLOCK_ERASE_2;
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busy <= wordProgramBusy or blockEraseBusy;
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------------------------------------------------------------------------------
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-- FSM: find next state
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------------------------------------------------------------------------------
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-- Table 4 p. 12
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process(writePulse, busy)
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begin
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case currentState is
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when READ_ARRAY | READ_ID_CODES | READ_QUERY | READ_STATUS =>
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case to_integer(memoryCommand) is
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when 16#FF# => nextState <= READ_ARRAY;
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when 16#90# => nextState <= READ_ID_CODES;
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when 16#98# => nextState <= READ_QUERY;
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when 16#70# => nextState <= READ_STATUS;
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when 16#E8# => nextState <= WRITE_BUFFER;
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when 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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when 16#20# => nextState <= BLOCK_ERASE_1;
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when 16#B8# => nextState <= CONFIG;
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when 16#60# => nextState <= PROG_LOCK_BITS;
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when 16#C0# => nextState <= PROG_PROT;
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when others => nextState <= READ_ARRAY;
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end case;
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when WORD_PROGRAM_1 =>
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nextState <= WORD_PROGRAM_2;
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when WORD_PROGRAM_2 =>
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nextState <= READ_ARRAY;
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when BLOCK_ERASE_1 =>
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if to_integer(memoryCommand) = 16#D0# then
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nextState <= BLOCK_ERASE_2;
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else
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nextState <= READ_ARRAY;
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end if;
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when BLOCK_ERASE_2 =>
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nextState <= READ_ARRAY;
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-- WHEN PROG_LOCK_BITS =>
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-- IF rising_edge(WENeg) THEN
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-- -- SECOND CYCLE CHECK
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-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN
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-- nextState<=READ_ARRAY;
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-- ELSE
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-- nextState <= BOTCH_LOCK;
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-- END IF;
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-- END IF;
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--
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-- WHEN PROG_LOCK_BITS_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN
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-- nextState<=READ_ARRAY_ERS_SUSP;
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-- ELSE
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-- nextState <= BOTCH_LOCK_ERS_SUSP;
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-- END IF;
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-- END IF;
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--
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--
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-- WHEN LOCK_DONE =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <= BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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--
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-- WHEN LOCK_DONE_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP;
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-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP;
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-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP;
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-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP;
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-- WHEN 16#D0# => nextState <= ERASE_BUSY;
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-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP;
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-- END CASE;
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-- END IF;
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--
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-- WHEN BOTCH_LOCK =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <= BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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--
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-- WHEN BOTCH_LOCK_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# =>
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-- nextState <= WORD_PROGRAM_1_ERS_SUSP;
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-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP;
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-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP;
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-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP;
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-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP;
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-- END CASE;
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-- END IF;
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--
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--
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-- WHEN BOTCH_ERS =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# =>
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-- nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <=BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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--
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--
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-- WHEN PROG_PROT =>
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-- IF rising_edge(WENeg) THEN
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-- nextState <= PROT_PROG_BUSY;
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-- END IF;
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--
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-- WHEN PROT_PROG_BUSY =>
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-- IF S_Reg(7)='1' THEN
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-- nextState <= PROT_PROG_DONE;
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-- ELSE
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-- nextState <= PROT_PROG_BUSY;
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-- END IF;
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--
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-- WHEN PROT_PROG_DONE =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <= BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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--
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-- WHEN WORD_PROGRAM_1 =>
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-- IF rising_edge(WENeg) THEN
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-- nextState <= PROG_BUSY;
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-- END IF;
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--
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-- WHEN WORD_PROGRAM_1_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- nextState <= PROG_BUSY_ERS_SUSP;
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-- END IF;
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--
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-- WHEN PROG_BUSY =>
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-- IF WDone THEN
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-- nextState<=PROGRAM_DONE;
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-- ELSIF rising_edge(WENeg) THEN
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-- IF data= 16#B0# THEN
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-- nextState <= READ_STATUS_PROG_SUSP;
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-- ELSE
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-- nextState <= PROG_BUSY;
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-- END IF;
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-- END IF;
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--
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-- WHEN PROG_BUSY_ERS_SUSP =>
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-- IF WDone THEN
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-- nextState<=PROGRAM_DONE_ERS_SUSP;
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-- ELSIF rising_edge(WENeg) THEN
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-- nextState <= PROG_BUSY_ERS_SUSP;
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-- END IF;
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--
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-- WHEN READ_STATUS_PROG_SUSP | READ_ARRAY_PROG_SUSP |
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-- READ_CONFIG_PROG_SUSP | READ_QUERY_PROG_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- --WHEN 16#D0# => nextState <= READ_ARRAY_PROG_SUSP;
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-- WHEN 16#D0# => nextState <= PROG_BUSY;
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-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_PROG_SUSP;
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-- WHEN 16#90# => nextState <= READ_CONFIG_PROG_SUSP;
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-- WHEN 16#98# => nextState <= READ_QUERY_PROG_SUSP;
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-- WHEN OTHERS => nextState <= READ_ARRAY_PROG_SUSP;
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-- END CASE;
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-- END IF;
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--
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-- WHEN PROGRAM_DONE =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <= BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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--
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-- WHEN PROGRAM_DONE_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP;
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-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_ERS_SUSP;
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-- WHEN 16#D0# => nextState <= ERASE_BUSY;
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-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP;
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-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP;
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-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP;
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-- END CASE;
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-- END IF;
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--
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--
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-- WHEN ERASE_BUSY =>
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-- IF rising_edge(WENeg) AND data= 16#B0# THEN
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-- nextState <= READ_STATUS_ERS_SUSP;
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-- ELSIF EDone AND ECount=31 THEN
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-- nextState<=ERASE_DONE;
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-- ELSE
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-- nextState <= ERASE_BUSY;
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-- END IF;
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--
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-- WHEN READ_STATUS_ERS_SUSP | READ_ARRAY_ERS_SUSP |
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-- READ_CONFIG_ERS_SUSP | READ_QUERY_ERS_SUSP =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <=WORD_PROGRAM_1_ERS_SUSP;
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-- WHEN 16#B0# | 16#70# | 16#80# =>
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-- nextState<= READ_STATUS_ERS_SUSP;
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-- WHEN 16#D0# => nextState <= ERASE_BUSY;
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-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP;
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-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP;
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-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP;
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-- END CASE;
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-- END IF;
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--
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-- WHEN ERASE_DONE =>
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-- IF rising_edge(WENeg) THEN
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-- CASE data IS
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-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1;
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-- WHEN 16#20# => nextState <= BLOCK_ERASE_1;
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-- WHEN 16#70# => nextState <= READ_STATUS;
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-- WHEN 16#90# => nextState <= READ_CONFIG;
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-- WHEN 16#98# => nextState <= READ_QUERY;
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-- WHEN 16#60# => nextState <= PROG_LOCK_BITS;
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-- WHEN 16#C0# => nextState <= PROG_PROT;
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-- WHEN OTHERS => nextState <= READ_ARRAY;
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-- END CASE;
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-- END IF;
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when others => nextState <= READ_ARRAY;
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end case;
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end process;
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------------------------------------------------------------------------------
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-- FSM: update state
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------------------------------------------------------------------------------
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process(RP_N, writePulseDelayed, busy)
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begin
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if RP_n = '0' then
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currentState <= READ_ARRAY;
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elsif falling_edge(writePulseDelayed) then
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currentState <= nextState;
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elsif falling_edge(busy) then
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currentState <= nextState;
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end if;
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end process;
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------------------------------------------------------------------------------
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-- STS
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------------------------------------------------------------------------------
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process
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begin
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STS <= '1';
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wait on busy;
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if rising_edge(busy) then
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STS <= '0' after T_W13;
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wait until falling_edge(busy);
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end if;
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end process;
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--############################################################################
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-- Storage
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------------------------------------------------------------------------------
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process(writePulse, A)
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variable memContent : memoryArray; -- much faster than using a signal
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variable loadMemFromFile : boolean := true;
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file memoryFile : text open read_mode is fileSpec;
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variable srecLine : line;
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variable srecChar : character;
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variable srecType : natural;
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variable srecAddrLength : natural;
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variable srecWordAscii : string(8 downto 1);
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variable srecLength : natural;
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variable srecAddress : natural;
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variable memoryAddress : natural;
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variable srecData : natural;
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function readNumber(hexString: string) return natural is
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variable currentCharPos: natural;
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variable intValue: natural;
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variable accValue: natural;
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begin
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accValue := 0;
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for index in hexString'range loop
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currentCharPos := character'pos(hexString(index));
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if currentCharPos <= character'pos('9') then
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intValue := currentCharPos - character'pos('0');
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else
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intValue := currentCharPos - character'pos('A') + 10;
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end if;
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accValue := accValue * 16 + intValue;
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end loop;
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return accValue;
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end readNumber;
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begin
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if loadMemFromFile then
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-- only happens at simulation start
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while not endfile(memoryFile) loop
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readline(memoryFile, srecLine);
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--report "-> " & srecLine.all;
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-- trim leading whitespaces
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while (not (srecLine'length=0)) and (srecLine(srecLine'left) = ' ') loop
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read(srecLine, srecChar);
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end loop;
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-- get record type
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if srecLine'length > 0 then
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read(srecLine, srecChar);
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if (srecChar = 'S') or (srecChar = 's') then
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read(srecLine, srecChar);
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srecType := character'pos(srecChar) - character'pos('0');
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--report "-> srec type: " & integer'image(srecType);
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srecAddrLength := srecType + 1;
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if (srecType >= 1) and (srecType <= 3) then
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-- get record length
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srecWordAscii := (others => '0');
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read(srecLine, srecWordAscii(2));
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read(srecLine, srecWordAscii(1));
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srecLength := readNumber(srecWordAscii);
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-- get record base address
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srecWordAscii := (others => '0');
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for index in 2*(srecAddrLength) downto 1 loop
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read(srecLine, srecWordAscii(index));
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end loop;
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srecAddress := readNumber(srecWordAscii);
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memoryAddress := srecAddress/2;
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-- get record data
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for index1 in 1 to (srecLength - srecAddrLength - 1) / 2 loop
|
|
srecWordAscii := (others => '0');
|
|
for index2 in 4 downto 1 loop
|
|
read(srecLine, srecWordAscii(index2));
|
|
end loop;
|
|
srecData := readNumber(srecWordAscii);
|
|
if memoryAddress < memoryLength then
|
|
memContent(memoryAddress) := std_ulogic_vector(to_unsigned(srecData, memoryWord'length));
|
|
end if;
|
|
memoryAddress := memoryAddress + 1;
|
|
end loop;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end loop;
|
|
loadMemFromFile := false;
|
|
else
|
|
-- normal functionality
|
|
if falling_edge(writePulse) then
|
|
-- program a word
|
|
if currentState = WORD_PROGRAM_1 then
|
|
memoryAddress := to_integer(A(A'high downto 1));
|
|
memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length);
|
|
memContent(memoryAddress) := std_ulogic_vector(DQ);
|
|
-- erase a block
|
|
elsif currentState = BLOCK_ERASE_1 then
|
|
memoryAddress := to_integer(A and not(to_unsigned(blockLength-1, A'length)));
|
|
for index in 0 to blockLength-1 loop
|
|
if memoryAddress < memoryLength then
|
|
memContent(memoryAddress) := (others => '1');
|
|
memoryAddress := memoryAddress + 1;
|
|
end if;
|
|
end loop;
|
|
end if;
|
|
end if;
|
|
-- update readout data
|
|
if A'event then
|
|
memoryAddress := to_integer(A(A'high downto 1));
|
|
memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length);
|
|
memoryDataWord <= memContent(memoryAddress) after T_R2;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(memoryDataWord, readPulse)
|
|
begin
|
|
if readPulse = '1' then
|
|
DQ <= std_logic_vector(memoryDataWord);
|
|
else
|
|
DQ <= (others => 'Z');
|
|
end if;
|
|
end process;
|
|
|
|
|
|
|
|
END ARCHITECTURE behav;
|
|
|