mirror of
https://github.com/Klagarge/Cursor.git
synced 2025-08-01 20:43:09 +00:00
5 lines
63 B
VHDL
5 lines
63 B
VHDL
ARCHITECTURE sim OF logic1 IS
|
|
BEGIN
|
|
logic_1 <= '1';
|
|
END sim;
|