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119 lines
3.2 KiB
VHDL
119 lines
3.2 KiB
VHDL
library Common;
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use Common.CommonLib.all;
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architecture pim of FIFO_bram is
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type mem_t is array (depth-1 downto 0) of std_ulogic_vector(dataIn'range);
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subtype mem_range_r is natural range requiredBitNb(depth)-1 downto 0;
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subtype ptr_range_r is natural range requiredBitNb(depth)+1-1 downto 0;
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signal mem : mem_t := (others => (others => '0'));
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signal full_int : std_logic;
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signal empty_int : std_logic;
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signal write_error : std_logic;
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signal read_error : std_logic;
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signal read_ptr : unsigned(ptr_range_r);
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signal read_ptr_next : unsigned(ptr_range_r);
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signal write_ptr : unsigned(ptr_range_r);
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signal write_ptr_next : unsigned(ptr_range_r);
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signal used_int : unsigned(ptr_range_r);
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begin
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-----------------------------------------------------------------------------
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-- Free / used
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-----------------------------------------------------------------------------
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fifo_count_proc: process(reset, clock)
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begin
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if reset = '1' then
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used_int <= (others => '0');
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elsif rising_edge(clock) then
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if write = '1' and full_int = '0' then
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used_int <= used_int + 1;
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end if;
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if read = '1' and empty_int = '0' then
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used_int <= used_int - 1;
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end if;
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-- Simultaneous read/write -> no change
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-- ignore full_int, since it is valid
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if write = '1' and read = '1' and empty_int = '0' then
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used_int <= used_int;
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end if;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- FIFO status
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-----------------------------------------------------------------------------
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full_int <= '1' when (write_ptr(write_ptr'left) /= read_ptr(read_ptr'left))
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and ((write_ptr(mem_range_r) = read_ptr(mem_range_r)))
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else '0';
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empty_int <= '1' when (write_ptr = read_ptr) else '0';
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full <= full_int;
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empty <= empty_int;
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write_ptr_next <= write_ptr + 1;
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read_ptr_next <= read_ptr + 1;
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-----------------------------------------------------------------------------
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-- FIFO pointers
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-----------------------------------------------------------------------------
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fifo_ptr_proc: process(reset, clock)
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begin
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if reset = '1' then
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write_ptr <= (others => '0');
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read_ptr <= (others => '0');
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write_error <= '0';
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read_error <= '0';
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elsif rising_edge(clock) then
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write_error <= '0';
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read_error <= '0';
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if write = '1' then
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if full_int = '0' or read = '1' then
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write_ptr <= write_ptr_next;
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else
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write_error <= '1';
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end if;
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end if;
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if read = '1' then
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if empty_int = '0' then
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read_ptr <= read_ptr_next;
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else
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read_error <= '1';
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end if;
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end if;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- FIFO RAM
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-----------------------------------------------------------------------------
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fifo_out_proc : process(clock)
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begin
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if rising_edge(clock) then
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dataOut <= mem(to_integer(read_ptr(mem_range_r)));
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end if;
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end process;
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fifo_in_proc : process(clock)
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begin
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if rising_edge(clock) then
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if write = '1' and full_int = '0' then
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mem(to_integer(write_ptr(mem_range_r))) <= dataIn;
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end if;
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end if;
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end process;
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end pim;
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