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51 lines
1.7 KiB
VHDL
51 lines
1.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program IS distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License along with
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-- this program. If not, see <http://www.gnu.org/licenses/>
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--------------------------------------------------------------------------------
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-- EdgeDetector
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-- Detect rising and falling edges of a signal.
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--
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-- Created on 2014-04-02
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--
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-- Version: 1.0
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-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
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--------------------------------------------------------------------------------
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ARCHITECTURE arch OF edgeDetector IS
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SIGNAL signal_s : std_ulogic;
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SIGNAL rising_detected_s : std_ulogic;
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SIGNAL falling_detected_s : std_ulogic;
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BEGIN
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-- sync
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reg : PROCESS (reset,clock)
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BEGIN
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IF reset = '1' THEN
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signal_s <= '0';
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ELSIF rising_edge(clock) THEN
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signal_s <= input;
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END IF;
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END PROCESS reg ;
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-- edge detection
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rising_detected_s <= input AND NOT signal_s;
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falling_detected_s <= NOT input AND signal_s;
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-- output
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rising_detected <= rising_detected_s;
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falling_detected <= falling_detected_s;
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END ARCHITECTURE arch;
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