mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-30 04:43:26 +00:00
2254 lines
27 KiB
Plaintext
2254 lines
27 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2090,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 370,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "button4"
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t "std_uLogic"
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o 1
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suid 2076,0
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)
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)
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uid 977,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 2
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suid 2077,0
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)
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)
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uid 979,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "encoderA"
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t "std_uLogic"
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o 3
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suid 2078,0
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)
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)
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uid 981,0
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)
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*17 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "encoderB"
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t "std_uLogic"
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o 4
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suid 2079,0
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)
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)
|
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uid 983,0
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)
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*18 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
|
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n "encoderI"
|
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t "std_uLogic"
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o 5
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suid 2080,0
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)
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)
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uid 985,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "go1"
|
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t "std_uLogic"
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o 6
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suid 2081,0
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)
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)
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uid 987,0
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)
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*20 (LogPort
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port (LogicalPort
|
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m 1
|
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decl (Decl
|
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n "go2"
|
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t "std_uLogic"
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o 7
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suid 2082,0
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)
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)
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uid 989,0
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)
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*21 (LogPort
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port (LogicalPort
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decl (Decl
|
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n "motorOn"
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t "std_uLogic"
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o 8
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suid 2083,0
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)
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)
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uid 991,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
|
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n "reset"
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t "std_ulogic"
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o 9
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suid 2084,0
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)
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)
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uid 993,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
|
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n "restart"
|
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t "std_uLogic"
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o 10
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suid 2085,0
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)
|
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)
|
|
uid 995,0
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)
|
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*24 (LogPort
|
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port (LogicalPort
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m 1
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decl (Decl
|
|
n "sensor1"
|
|
t "std_uLogic"
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o 11
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suid 2086,0
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)
|
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)
|
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uid 997,0
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)
|
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*25 (LogPort
|
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port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "sensor2"
|
|
t "std_uLogic"
|
|
o 12
|
|
suid 2087,0
|
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)
|
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)
|
|
uid 999,0
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)
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*26 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "side1"
|
|
t "std_uLogic"
|
|
o 13
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|
suid 2088,0
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)
|
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)
|
|
uid 1001,0
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)
|
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*27 (LogPort
|
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port (LogicalPort
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decl (Decl
|
|
n "side2"
|
|
t "std_uLogic"
|
|
o 14
|
|
suid 2089,0
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)
|
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)
|
|
uid 1003,0
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)
|
|
*28 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testMode"
|
|
t "std_uLogic"
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|
o 15
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suid 2090,0
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)
|
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)
|
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uid 1005,0
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)
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]
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)
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pdm (PhysicalDM
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uid 386,0
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optionalChildren [
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*29 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *30 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 303,0
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optionalChildren [
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*31 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 306,0
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)
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*32 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 308,0
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)
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*33 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 310,0
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)
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*34 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 978,0
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)
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*35 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 980,0
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)
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*36 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 982,0
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)
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*37 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 984,0
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)
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*38 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 986,0
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)
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*39 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 988,0
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)
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*40 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 990,0
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)
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*41 (MRCItem
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litem &21
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pos 7
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dimension 20
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uid 992,0
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)
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*42 (MRCItem
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litem &22
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pos 8
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dimension 20
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uid 994,0
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)
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*43 (MRCItem
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litem &23
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pos 9
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dimension 20
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uid 996,0
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)
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*44 (MRCItem
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litem &24
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pos 10
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dimension 20
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uid 998,0
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)
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*45 (MRCItem
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litem &25
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pos 11
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dimension 20
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uid 1000,0
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)
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*46 (MRCItem
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litem &26
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pos 12
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dimension 20
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uid 1002,0
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)
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*47 (MRCItem
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litem &27
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pos 13
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dimension 20
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uid 1004,0
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)
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*48 (MRCItem
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litem &28
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pos 14
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dimension 20
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uid 1006,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 304,0
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optionalChildren [
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*49 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 312,0
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)
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*50 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 316,0
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)
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*51 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 318,0
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)
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*52 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 320,0
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)
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*53 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 322,0
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)
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*54 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 324,0
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)
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*55 (MRCItem
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litem &12
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pos 6
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dimension 50
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|
uid 326,0
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)
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*56 (MRCItem
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litem &13
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pos 7
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dimension 80
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uid 328,0
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)
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]
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)
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fixedCol 4
|
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fixedRow 2
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name "Ports"
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uid 302,0
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vaOverrides [
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]
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)
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]
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)
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uid 369,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *57 (LEmptyRow
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)
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uid 388,0
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optionalChildren [
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*58 (RefLabelRowHdr
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)
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*59 (TitleRowHdr
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)
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*60 (FilterRowHdr
|
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)
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*61 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*62 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*63 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*64 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*65 (TypeColHdr
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tm "GenericTypeColHdrMgr"
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)
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*66 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
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*67 (PragmaColHdr
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tm "GenericPragmaColHdrMgr"
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)
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*68 (EolColHdr
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tm "GenericEolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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uid 389,0
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optionalChildren [
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*69 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *70 (MRCItem
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litem &57
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pos 3
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dimension 20
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)
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uid 345,0
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optionalChildren [
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*71 (MRCItem
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litem &58
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pos 0
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dimension 20
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uid 348,0
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)
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*72 (MRCItem
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litem &59
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pos 1
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dimension 23
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uid 350,0
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)
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*73 (MRCItem
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litem &60
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pos 2
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hidden 1
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dimension 20
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uid 352,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 346,0
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optionalChildren [
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*74 (MRCItem
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litem &61
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pos 0
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dimension 20
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uid 354,0
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)
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*75 (MRCItem
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litem &63
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pos 1
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dimension 50
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uid 358,0
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)
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*76 (MRCItem
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litem &64
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pos 2
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dimension 100
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uid 360,0
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)
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*77 (MRCItem
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litem &65
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pos 3
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dimension 100
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uid 362,0
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)
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*78 (MRCItem
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litem &66
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pos 4
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dimension 50
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uid 364,0
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)
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*79 (MRCItem
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litem &67
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pos 5
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dimension 50
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|
uid 366,0
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)
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*80 (MRCItem
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litem &68
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pos 6
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dimension 80
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uid 368,0
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)
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]
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)
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 344,0
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vaOverrides [
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]
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)
|
|
]
|
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)
|
|
uid 387,0
|
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type 1
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)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Mon"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Monday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "cursor_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.11.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "08:13:23"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Cursor_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Cursor_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "cursor_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Nov"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "November"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "/usr/opt/Modelsim/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "08:13:23"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "cursor_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "VhdlLangMgr"
|
|
uid 106,0
|
|
optionalChildren [
|
|
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uid 8,0
|
|
optionalChildren [
|
|
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|
uid 902,0
|
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ps "OnEdgeStrategy"
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|
shape (Triangle
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uid 903,0
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va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "28625,5250,29375,6000"
|
|
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|
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tg (CPTG
|
|
uid 904,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "28300,7000,29700,12800"
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st "button4"
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ju 2
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|
blo "29500,7000"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "Courier New,8,0"
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st "button4 : OUT std_uLogic ;
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thePort (LogicalPort
|
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m 1
|
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decl (Decl
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n "button4"
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t "std_uLogic"
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uid 907,0
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 909,0
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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font "Verdana,12,0"
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xt "34300,7000,35700,10800"
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st "clock"
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blo "35500,7000"
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tm "CptPortNameMgr"
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dt (MLText
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uid 911,0
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va (VaSet
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font "Courier New,8,0"
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xt "44000,5000,61000,5800"
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st "clock : OUT std_ulogic ;
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|
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)
|
|
thePort (LogicalPort
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|
m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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suid 2077,0
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*84 (CptPort
|
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uid 912,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 913,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 914,0
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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font "Verdana,12,0"
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blo "65500,7000"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 916,0
|
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va (VaSet
|
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font "Courier New,8,0"
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)
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st "encoderA : OUT std_uLogic ;
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"
|
|
)
|
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thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
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n "encoderA"
|
|
t "std_uLogic"
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suid 2078,0
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)
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*85 (CptPort
|
|
uid 917,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 918,0
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va (VaSet
|
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
|
|
uid 919,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
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uid 920,0
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va (VaSet
|
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font "Verdana,12,0"
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)
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xt "62300,7000,63700,13700"
|
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st "encoderB"
|
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ju 2
|
|
blo "63500,7000"
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tm "CptPortNameMgr"
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)
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dt (MLText
|
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uid 921,0
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va (VaSet
|
|
font "Courier New,8,0"
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)
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xt "44000,6600,61000,7400"
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st "encoderB : OUT std_uLogic ;
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"
|
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)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "encoderB"
|
|
t "std_uLogic"
|
|
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|
|
suid 2079,0
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)
|
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)
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*86 (CptPort
|
|
uid 922,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 923,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 924,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
|
uid 925,0
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ro 270
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va (VaSet
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font "Verdana,12,0"
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)
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st "encoderI"
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ju 2
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|
blo "61500,7000"
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tm "CptPortNameMgr"
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)
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dt (MLText
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|
uid 926,0
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va (VaSet
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font "Courier New,8,0"
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st "encoderI : OUT std_uLogic ;
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|
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)
|
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thePort (LogicalPort
|
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m 1
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decl (Decl
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n "encoderI"
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t "std_uLogic"
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suid 2080,0
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)
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)
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*87 (CptPort
|
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uid 927,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 928,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 929,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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uid 930,0
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ro 270
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va (VaSet
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font "Verdana,12,0"
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)
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st "go1"
|
|
ju 2
|
|
blo "25500,7000"
|
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tm "CptPortNameMgr"
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)
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dt (MLText
|
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uid 931,0
|
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va (VaSet
|
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font "Courier New,8,0"
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)
|
|
xt "44000,8200,61000,9000"
|
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st "go1 : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
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decl (Decl
|
|
n "go1"
|
|
t "std_uLogic"
|
|
o 6
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suid 2081,0
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)
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)
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*88 (CptPort
|
|
uid 932,0
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ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 933,0
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va (VaSet
|
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
|
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uid 934,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
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uid 935,0
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ro 270
|
|
va (VaSet
|
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font "Verdana,12,0"
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)
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xt "26300,7000,27700,10200"
|
|
st "go2"
|
|
ju 2
|
|
blo "27500,7000"
|
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tm "CptPortNameMgr"
|
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)
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)
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dt (MLText
|
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uid 936,0
|
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va (VaSet
|
|
font "Courier New,8,0"
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)
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xt "44000,9000,61000,9800"
|
|
st "go2 : OUT std_uLogic ;
|
|
"
|
|
)
|
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thePort (LogicalPort
|
|
m 1
|
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decl (Decl
|
|
n "go2"
|
|
t "std_uLogic"
|
|
o 7
|
|
suid 2082,0
|
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)
|
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)
|
|
)
|
|
*89 (CptPort
|
|
uid 937,0
|
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ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 938,0
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ro 180
|
|
va (VaSet
|
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vasetType 1
|
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fg "0,65535,0"
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xt "78625,5250,79375,6000"
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)
|
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tg (CPTG
|
|
uid 939,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 940,0
|
|
ro 270
|
|
va (VaSet
|
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font "Verdana,12,0"
|
|
)
|
|
xt "78300,7000,79700,13300"
|
|
st "motorOn"
|
|
ju 2
|
|
blo "79500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 941,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,1800,61000,2600"
|
|
st "motorOn : IN std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "motorOn"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 2083,0
|
|
)
|
|
)
|
|
)
|
|
*90 (CptPort
|
|
uid 942,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 943,0
|
|
va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
|
|
)
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|
xt "36625,5250,37375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 944,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 945,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "36300,7000,37700,11100"
|
|
st "reset"
|
|
ju 2
|
|
blo "37500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 946,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
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|
)
|
|
xt "44000,9800,61000,10600"
|
|
st "reset : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 2084,0
|
|
)
|
|
)
|
|
)
|
|
*91 (CptPort
|
|
uid 947,0
|
|
ps "OnEdgeStrategy"
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|
shape (Triangle
|
|
uid 948,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
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|
)
|
|
xt "22625,5250,23375,6000"
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|
)
|
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tg (CPTG
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blo "23500,7000"
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blo "71500,7000"
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tm "CptPortNameMgr"
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blo "69500,7000"
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va (VaSet
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blo "77500,7000"
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blo "75500,7000"
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tg (CPTG
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blo "33500,7000"
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