mirror of
https://github.com/Klagarge/Cursor.git
synced 2025-04-02 23:16:03 +00:00
5397 lines
62 KiB
Plaintext
5397 lines
62 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
|
||
unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
|
||
unitName "numeric_std"
|
||
)
|
||
(DmPackageRef
|
||
library "gates"
|
||
unitName "gates"
|
||
)
|
||
(DmPackageRef
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||
library "ieee"
|
||
unitName "NUMERIC_SIGNED"
|
||
)
|
||
]
|
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instances [
|
||
(Instance
|
||
name "U_0"
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duLibraryName "Cursor"
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||
duName "cpt1bit"
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elements [
|
||
]
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mwi 0
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uid 251,0
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)
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(Instance
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name "U_1"
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duLibraryName "Cursor"
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||
duName "cpt1bit"
|
||
elements [
|
||
]
|
||
mwi 0
|
||
uid 261,0
|
||
)
|
||
(Instance
|
||
name "U_2"
|
||
duLibraryName "Cursor"
|
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duName "cpt1bit"
|
||
elements [
|
||
]
|
||
mwi 0
|
||
uid 307,0
|
||
)
|
||
(Instance
|
||
name "U_3"
|
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duLibraryName "Cursor"
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||
duName "cpt1bit"
|
||
elements [
|
||
]
|
||
mwi 0
|
||
uid 347,0
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)
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||
]
|
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libraryRefs [
|
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"ieee"
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"gates"
|
||
]
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||
)
|
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version "32.1"
|
||
appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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||
model (BlockDiag
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VExpander (VariableExpander
|
||
vvMap [
|
||
(vvPair
|
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variable "HDLDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hdl"
|
||
)
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||
(vvPair
|
||
variable "HDSDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds"
|
||
)
|
||
(vvPair
|
||
variable "SideDataDesignDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit\\struct.bd.info"
|
||
)
|
||
(vvPair
|
||
variable "SideDataUserDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit\\struct.bd.user"
|
||
)
|
||
(vvPair
|
||
variable "SourceDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds"
|
||
)
|
||
(vvPair
|
||
variable "appl"
|
||
value "HDL Designer"
|
||
)
|
||
(vvPair
|
||
variable "arch_name"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "concat_file"
|
||
value "concatenated"
|
||
)
|
||
(vvPair
|
||
variable "config"
|
||
value "%(unit)_%(view)_config"
|
||
)
|
||
(vvPair
|
||
variable "d"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit"
|
||
)
|
||
(vvPair
|
||
variable "d_logical"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit"
|
||
)
|
||
(vvPair
|
||
variable "date"
|
||
value "21.12.2021"
|
||
)
|
||
(vvPair
|
||
variable "day"
|
||
value "mar."
|
||
)
|
||
(vvPair
|
||
variable "day_long"
|
||
value "mardi"
|
||
)
|
||
(vvPair
|
||
variable "dd"
|
||
value "21"
|
||
)
|
||
(vvPair
|
||
variable "entity_name"
|
||
value "cpt4bit"
|
||
)
|
||
(vvPair
|
||
variable "ext"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "f"
|
||
value "struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "f_logical"
|
||
value "struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "f_noext"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_author"
|
||
value "remi"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_date"
|
||
value "21.12.2021"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_group"
|
||
value "UNKNOWN"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_host"
|
||
value "MARVIN"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_time"
|
||
value "13:37:10"
|
||
)
|
||
(vvPair
|
||
variable "group"
|
||
value "UNKNOWN"
|
||
)
|
||
(vvPair
|
||
variable "host"
|
||
value "MARVIN"
|
||
)
|
||
(vvPair
|
||
variable "language"
|
||
value "VHDL"
|
||
)
|
||
(vvPair
|
||
variable "library"
|
||
value "Cursor"
|
||
)
|
||
(vvPair
|
||
variable "library_downstream_ModelSimCompiler"
|
||
value "$SCRATCH_DIR/Cursor/work"
|
||
)
|
||
(vvPair
|
||
variable "mm"
|
||
value "12"
|
||
)
|
||
(vvPair
|
||
variable "module_name"
|
||
value "cpt4bit"
|
||
)
|
||
(vvPair
|
||
variable "month"
|
||
value "d<>c."
|
||
)
|
||
(vvPair
|
||
variable "month_long"
|
||
value "d<>cembre"
|
||
)
|
||
(vvPair
|
||
variable "p"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit\\struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "p_logical"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor\\hds\\cpt4bit\\struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "package_name"
|
||
value "<Undefined Variable>"
|
||
)
|
||
(vvPair
|
||
variable "project_name"
|
||
value "hds"
|
||
)
|
||
(vvPair
|
||
variable "series"
|
||
value "HDL Designer Series"
|
||
)
|
||
(vvPair
|
||
variable "this_ext"
|
||
value "bd"
|
||
)
|
||
(vvPair
|
||
variable "this_file"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "this_file_logical"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "time"
|
||
value "13:37:10"
|
||
)
|
||
(vvPair
|
||
variable "unit"
|
||
value "cpt4bit"
|
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)
|
||
(vvPair
|
||
variable "user"
|
||
value "remi"
|
||
)
|
||
(vvPair
|
||
variable "version"
|
||
value "2019.2 (Build 5)"
|
||
)
|
||
(vvPair
|
||
variable "view"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "year"
|
||
value "2021"
|
||
)
|
||
(vvPair
|
||
variable "yy"
|
||
value "21"
|
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)
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]
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)
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LanguageMgr "Vhdl2008LangMgr"
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uid 164,0
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optionalChildren [
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uid 9,0
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shape (CompositeShape
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)
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)
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stc 0
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sf 1
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tg (WTG
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uid 13,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 14,0
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va (VaSet
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blo "-3000,29400"
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tm "WireNameMgr"
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uid 21,0
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lang 11
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decl (Decl
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suid 1,0
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declText (MLText
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va (VaSet
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uid 23,0
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shape (CompositeShape
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tg (WTG
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uid 27,0
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ps "PortIoTextPlaceStrategy"
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uid 28,0
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va (VaSet
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blo "-5000,76400"
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tm "WireNameMgr"
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lang 11
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decl (Decl
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declText (MLText
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va (VaSet
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font "Courier New,8,0"
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uid 37,0
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shape (CompositeShape
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uid 38,0
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stc 0
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sf 1
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tg (WTG
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uid 41,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 42,0
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va (VaSet
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blo "63000,26400"
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tm "WireNameMgr"
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lang 11
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decl (Decl
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declText (MLText
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va (VaSet
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)
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||
xt "22000,-1000,36000,-200"
|
||
st "SIGNAL RCOi2 : std_ulogic
|
||
"
|
||
)
|
||
)
|
||
*76 (Net
|
||
uid 417,0
|
||
lang 11
|
||
decl (Decl
|
||
n "RCOi3"
|
||
t "std_ulogic"
|
||
o 10
|
||
suid 10,0
|
||
)
|
||
declText (MLText
|
||
uid 418,0
|
||
va (VaSet
|
||
font "Courier New,8,0"
|
||
)
|
||
xt "22000,-200,36000,600"
|
||
st "SIGNAL RCOi3 : std_ulogic
|
||
"
|
||
)
|
||
)
|
||
*77 (Wire
|
||
uid 15,0
|
||
shape (OrthoPolyLine
|
||
uid 16,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "0,29000,10000,29000"
|
||
pts [
|
||
"0,29000"
|
||
"10000,29000"
|
||
]
|
||
)
|
||
start &1
|
||
ss 0
|
||
sat 32
|
||
eat 16
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 19,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 20,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "2000,27800,5400,29000"
|
||
st "clock"
|
||
blo "2000,28800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*78 (Wire
|
||
uid 29,0
|
||
shape (OrthoPolyLine
|
||
uid 30,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "-2000,73750,34000,76000"
|
||
pts [
|
||
"-2000,76000"
|
||
"34000,76000"
|
||
"34000,73750"
|
||
]
|
||
)
|
||
start &3
|
||
end &64
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 33,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 34,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "0,74800,2200,76000"
|
||
st "eni"
|
||
blo "0,75800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &4
|
||
)
|
||
*79 (Wire
|
||
uid 43,0
|
||
optionalChildren [
|
||
*80 (Ripper
|
||
uid 305,0
|
||
ps "OnConnectorStrategy"
|
||
shape (Line2D
|
||
pts [
|
||
"51000,26000"
|
||
"50000,25000"
|
||
]
|
||
uid 306,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "50000,25000,51000,26000"
|
||
)
|
||
)
|
||
*81 (Ripper
|
||
uid 391,0
|
||
ps "OnConnectorStrategy"
|
||
shape (Line2D
|
||
pts [
|
||
"51000,26000"
|
||
"50000,27000"
|
||
]
|
||
uid 392,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "50000,26000,51000,27000"
|
||
)
|
||
)
|
||
*82 (Ripper
|
||
uid 397,0
|
||
ps "OnConnectorStrategy"
|
||
shape (Line2D
|
||
pts [
|
||
"53000,26000"
|
||
"52000,27000"
|
||
]
|
||
uid 398,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "52000,26000,53000,27000"
|
||
)
|
||
)
|
||
*83 (Ripper
|
||
uid 403,0
|
||
ps "OnConnectorStrategy"
|
||
shape (Line2D
|
||
pts [
|
||
"54000,26000"
|
||
"55000,27000"
|
||
]
|
||
uid 404,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "54000,26000,55000,27000"
|
||
)
|
||
)
|
||
]
|
||
shape (OrthoPolyLine
|
||
uid 44,0
|
||
va (VaSet
|
||
vasetType 3
|
||
lineWidth 2
|
||
)
|
||
xt "50000,26000,60000,26000"
|
||
pts [
|
||
"60000,26000"
|
||
"50000,26000"
|
||
]
|
||
)
|
||
start &5
|
||
sat 32
|
||
eat 16
|
||
sty 1
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 47,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 48,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "59000,24800,65200,26000"
|
||
st "Qi : (3:0)"
|
||
blo "59000,25800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &6
|
||
)
|
||
*84 (Wire
|
||
uid 57,0
|
||
shape (OrthoPolyLine
|
||
uid 58,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "0,16000,10000,16000"
|
||
pts [
|
||
"0,16000"
|
||
"10000,16000"
|
||
]
|
||
)
|
||
start &7
|
||
sat 32
|
||
eat 16
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 61,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 62,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "2000,14800,4700,16000"
|
||
st "RaZ"
|
||
blo "2000,15800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &8
|
||
)
|
||
*85 (Wire
|
||
uid 71,0
|
||
shape (OrthoPolyLine
|
||
uid 72,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "34000,5000,58000,10250"
|
||
pts [
|
||
"58000,5000"
|
||
"34000,5000"
|
||
"34000,10250"
|
||
]
|
||
)
|
||
start &9
|
||
end &31
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 75,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 76,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "57000,3800,60400,5000"
|
||
st "RCOi"
|
||
blo "57000,4800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &10
|
||
)
|
||
*86 (Wire
|
||
uid 85,0
|
||
shape (OrthoPolyLine
|
||
uid 86,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "0,27000,10000,27000"
|
||
pts [
|
||
"0,27000"
|
||
"10000,27000"
|
||
]
|
||
)
|
||
start &11
|
||
sat 32
|
||
eat 16
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 89,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 90,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "2000,25800,5300,27000"
|
||
st "reset"
|
||
blo "2000,26800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &12
|
||
)
|
||
*87 (Wire
|
||
uid 99,0
|
||
shape (OrthoPolyLine
|
||
uid 100,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "0,13000,10000,13000"
|
||
pts [
|
||
"0,13000"
|
||
"10000,13000"
|
||
]
|
||
)
|
||
start &13
|
||
sat 32
|
||
eat 16
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 103,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 104,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "2000,11800,3900,13000"
|
||
st "up"
|
||
blo "2000,12800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &14
|
||
)
|
||
*88 (Wire
|
||
uid 301,0
|
||
shape (OrthoPolyLine
|
||
uid 302,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "39750,16000,50000,25000"
|
||
pts [
|
||
"39750,16000"
|
||
"50000,16000"
|
||
"50000,25000"
|
||
]
|
||
)
|
||
start &29
|
||
end &80
|
||
sat 32
|
||
eat 32
|
||
sl "(3)"
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 303,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 304,0
|
||
va (VaSet
|
||
)
|
||
xt "41750,14800,45150,16000"
|
||
st "Qi(3)"
|
||
blo "41750,15800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &6
|
||
)
|
||
*89 (Wire
|
||
uid 387,0
|
||
shape (OrthoPolyLine
|
||
uid 388,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "39750,27000,50000,32000"
|
||
pts [
|
||
"39750,32000"
|
||
"50000,32000"
|
||
"50000,27000"
|
||
]
|
||
)
|
||
start &41
|
||
end &81
|
||
sat 32
|
||
eat 32
|
||
sl "(2)"
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 389,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 390,0
|
||
va (VaSet
|
||
)
|
||
xt "41750,30800,45150,32000"
|
||
st "Qi(2)"
|
||
blo "41750,31800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &6
|
||
)
|
||
*90 (Wire
|
||
uid 393,0
|
||
shape (OrthoPolyLine
|
||
uid 394,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "39750,27000,52000,48000"
|
||
pts [
|
||
"39750,48000"
|
||
"52000,48000"
|
||
"52000,27000"
|
||
]
|
||
)
|
||
start &53
|
||
end &82
|
||
sat 32
|
||
eat 32
|
||
sl "(1)"
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 395,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 396,0
|
||
va (VaSet
|
||
)
|
||
xt "41750,46800,45150,48000"
|
||
st "Qi(1)"
|
||
blo "41750,47800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &6
|
||
)
|
||
*91 (Wire
|
||
uid 399,0
|
||
shape (OrthoPolyLine
|
||
uid 400,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "39750,27000,55000,64000"
|
||
pts [
|
||
"39750,64000"
|
||
"55000,64000"
|
||
"55000,27000"
|
||
]
|
||
)
|
||
start &65
|
||
end &83
|
||
sat 32
|
||
eat 32
|
||
sl "(0)"
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 401,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 402,0
|
||
va (VaSet
|
||
)
|
||
xt "41750,62800,45150,64000"
|
||
st "Qi(0)"
|
||
blo "41750,63800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &6
|
||
)
|
||
*92 (Wire
|
||
uid 407,0
|
||
shape (OrthoPolyLine
|
||
uid 408,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "34000,57750,34000,58250"
|
||
pts [
|
||
"34000,58250"
|
||
"34000,57750"
|
||
]
|
||
)
|
||
start &67
|
||
end &52
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 409,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 410,0
|
||
ro 270
|
||
va (VaSet
|
||
)
|
||
xt "32800,53250,34000,57350"
|
||
st "RCOi1"
|
||
blo "33800,57350"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &74
|
||
)
|
||
*93 (Wire
|
||
uid 413,0
|
||
shape (OrthoPolyLine
|
||
uid 414,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "34000,41750,34000,42250"
|
||
pts [
|
||
"34000,42250"
|
||
"34000,41750"
|
||
]
|
||
)
|
||
start &55
|
||
end &40
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 415,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 416,0
|
||
ro 270
|
||
va (VaSet
|
||
)
|
||
xt "32800,37250,34000,41350"
|
||
st "RCOi2"
|
||
blo "33800,41350"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &75
|
||
)
|
||
*94 (Wire
|
||
uid 419,0
|
||
shape (OrthoPolyLine
|
||
uid 420,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "34000,25750,34000,26250"
|
||
pts [
|
||
"34000,26250"
|
||
"34000,25750"
|
||
]
|
||
)
|
||
start &43
|
||
end &28
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 421,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 422,0
|
||
ro 270
|
||
va (VaSet
|
||
)
|
||
xt "32800,21250,34000,25350"
|
||
st "RCOi3"
|
||
blo "33800,25350"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &76
|
||
)
|
||
*95 (Wire
|
||
uid 425,0
|
||
shape (OrthoPolyLine
|
||
uid 426,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,14000,27250,14000"
|
||
pts [
|
||
"27250,14000"
|
||
"21000,14000"
|
||
]
|
||
)
|
||
start &33
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 429,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 430,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,12800,25150,14000"
|
||
st "up"
|
||
blo "23250,13800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &14
|
||
)
|
||
*96 (Wire
|
||
uid 433,0
|
||
shape (OrthoPolyLine
|
||
uid 434,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,16000,27250,16000"
|
||
pts [
|
||
"27250,16000"
|
||
"21000,16000"
|
||
]
|
||
)
|
||
start &30
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 437,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 438,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,14800,25950,16000"
|
||
st "RaZ"
|
||
blo "23250,15800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &8
|
||
)
|
||
*97 (Wire
|
||
uid 441,0
|
||
shape (OrthoPolyLine
|
||
uid 442,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,21000,27250,21000"
|
||
pts [
|
||
"27250,21000"
|
||
"21000,21000"
|
||
]
|
||
)
|
||
start &27
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 445,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 446,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,19800,25650,21000"
|
||
st "clock"
|
||
blo "22250,20800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*98 (Wire
|
||
uid 449,0
|
||
shape (OrthoPolyLine
|
||
uid 450,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,22000,27250,22000"
|
||
pts [
|
||
"27250,22000"
|
||
"21000,22000"
|
||
]
|
||
)
|
||
start &32
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 453,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 454,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,20800,25550,22000"
|
||
st "reset"
|
||
blo "22250,21800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &12
|
||
)
|
||
*99 (Wire
|
||
uid 455,0
|
||
shape (OrthoPolyLine
|
||
uid 456,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,30000,27250,30000"
|
||
pts [
|
||
"27250,30000"
|
||
"21000,30000"
|
||
]
|
||
)
|
||
start &45
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 461,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 462,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,28800,25150,30000"
|
||
st "up"
|
||
blo "23250,29800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &14
|
||
)
|
||
*100 (Wire
|
||
uid 463,0
|
||
shape (OrthoPolyLine
|
||
uid 464,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,37000,27250,37000"
|
||
pts [
|
||
"27250,37000"
|
||
"21000,37000"
|
||
]
|
||
)
|
||
start &39
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 469,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 470,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,35800,25650,37000"
|
||
st "clock"
|
||
blo "22250,36800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*101 (Wire
|
||
uid 471,0
|
||
shape (OrthoPolyLine
|
||
uid 472,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,38000,27250,38000"
|
||
pts [
|
||
"27250,38000"
|
||
"21000,38000"
|
||
]
|
||
)
|
||
start &44
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 477,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 478,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,36800,25550,38000"
|
||
st "reset"
|
||
blo "22250,37800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &12
|
||
)
|
||
*102 (Wire
|
||
uid 479,0
|
||
shape (OrthoPolyLine
|
||
uid 480,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,32000,27250,32000"
|
||
pts [
|
||
"27250,32000"
|
||
"21000,32000"
|
||
]
|
||
)
|
||
start &42
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 485,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 486,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,30800,25950,32000"
|
||
st "RaZ"
|
||
blo "23250,31800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &8
|
||
)
|
||
*103 (Wire
|
||
uid 487,0
|
||
shape (OrthoPolyLine
|
||
uid 488,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,46000,27250,46000"
|
||
pts [
|
||
"27250,46000"
|
||
"21000,46000"
|
||
]
|
||
)
|
||
start &57
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 493,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 494,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,44800,25150,46000"
|
||
st "up"
|
||
blo "23250,45800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &14
|
||
)
|
||
*104 (Wire
|
||
uid 495,0
|
||
shape (OrthoPolyLine
|
||
uid 496,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,53000,27250,53000"
|
||
pts [
|
||
"27250,53000"
|
||
"21000,53000"
|
||
]
|
||
)
|
||
start &51
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 501,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 502,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,51800,25650,53000"
|
||
st "clock"
|
||
blo "22250,52800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*105 (Wire
|
||
uid 503,0
|
||
shape (OrthoPolyLine
|
||
uid 504,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,54000,27250,54000"
|
||
pts [
|
||
"27250,54000"
|
||
"21000,54000"
|
||
]
|
||
)
|
||
start &56
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 509,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 510,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,52800,25550,54000"
|
||
st "reset"
|
||
blo "22250,53800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &12
|
||
)
|
||
*106 (Wire
|
||
uid 511,0
|
||
shape (OrthoPolyLine
|
||
uid 512,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,48000,27250,48000"
|
||
pts [
|
||
"27250,48000"
|
||
"21000,48000"
|
||
]
|
||
)
|
||
start &54
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 517,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 518,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,46800,25950,48000"
|
||
st "RaZ"
|
||
blo "23250,47800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &8
|
||
)
|
||
*107 (Wire
|
||
uid 519,0
|
||
shape (OrthoPolyLine
|
||
uid 520,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,62000,27250,62000"
|
||
pts [
|
||
"27250,62000"
|
||
"21000,62000"
|
||
]
|
||
)
|
||
start &69
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 525,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 526,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,60800,25150,62000"
|
||
st "up"
|
||
blo "23250,61800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &14
|
||
)
|
||
*108 (Wire
|
||
uid 527,0
|
||
shape (OrthoPolyLine
|
||
uid 528,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,69000,27250,69000"
|
||
pts [
|
||
"27250,69000"
|
||
"21000,69000"
|
||
]
|
||
)
|
||
start &63
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 533,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 534,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,67800,25650,69000"
|
||
st "clock"
|
||
blo "22250,68800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*109 (Wire
|
||
uid 535,0
|
||
shape (OrthoPolyLine
|
||
uid 536,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,70000,27250,70000"
|
||
pts [
|
||
"27250,70000"
|
||
"21000,70000"
|
||
]
|
||
)
|
||
start &68
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 541,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 542,0
|
||
va (VaSet
|
||
)
|
||
xt "22250,68800,25550,70000"
|
||
st "reset"
|
||
blo "22250,69800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &12
|
||
)
|
||
*110 (Wire
|
||
uid 543,0
|
||
shape (OrthoPolyLine
|
||
uid 544,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,64000,27250,64000"
|
||
pts [
|
||
"27250,64000"
|
||
"21000,64000"
|
||
]
|
||
)
|
||
start &66
|
||
sat 32
|
||
eat 16
|
||
stc 0
|
||
st 0
|
||
si 0
|
||
tg (WTG
|
||
uid 549,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 550,0
|
||
va (VaSet
|
||
)
|
||
xt "23250,62800,25950,64000"
|
||
st "RaZ"
|
||
blo "23250,63800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &8
|
||
)
|
||
]
|
||
bg "65535,65535,65535"
|
||
grid (Grid
|
||
origin "0,0"
|
||
isVisible 1
|
||
isActive 1
|
||
xSpacing 1000
|
||
xySpacing 1000
|
||
xShown 1
|
||
yShown 1
|
||
color "26368,26368,26368"
|
||
)
|
||
packageList *111 (PackageList
|
||
uid 153,0
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*112 (Text
|
||
uid 154,0
|
||
va (VaSet
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "0,0,7600,1200"
|
||
st "Package List"
|
||
blo "0,1000"
|
||
)
|
||
*113 (MLText
|
||
uid 155,0
|
||
va (VaSet
|
||
)
|
||
xt "0,1200,19000,8400"
|
||
st "LIBRARY ieee;
|
||
USE ieee.std_logic_1164.all;
|
||
USE ieee.numeric_std.all;
|
||
LIBRARY gates;
|
||
USE gates.gates.all;
|
||
USE ieee.NUMERIC_SIGNED.all;"
|
||
tm "PackageList"
|
||
)
|
||
]
|
||
)
|
||
compDirBlock (MlTextGroup
|
||
uid 156,0
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*114 (Text
|
||
uid 157,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "20000,0,30800,1200"
|
||
st "Compiler Directives"
|
||
blo "20000,1000"
|
||
)
|
||
*115 (Text
|
||
uid 158,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "20000,1200,33100,2400"
|
||
st "Pre-module directives:"
|
||
blo "20000,2200"
|
||
)
|
||
*116 (MLText
|
||
uid 159,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "20000,2400,32100,4800"
|
||
st "`resetall
|
||
`timescale 1ns/10ps"
|
||
tm "BdCompilerDirectivesTextMgr"
|
||
)
|
||
*117 (Text
|
||
uid 160,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "20000,4800,33700,6000"
|
||
st "Post-module directives:"
|
||
blo "20000,5800"
|
||
)
|
||
*118 (MLText
|
||
uid 161,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "20000,0,20000,0"
|
||
tm "BdCompilerDirectivesTextMgr"
|
||
)
|
||
*119 (Text
|
||
uid 162,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "20000,6000,33200,7200"
|
||
st "End-module directives:"
|
||
blo "20000,7000"
|
||
)
|
||
*120 (MLText
|
||
uid 163,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "20000,7200,20000,7200"
|
||
tm "BdCompilerDirectivesTextMgr"
|
||
)
|
||
]
|
||
associable 1
|
||
)
|
||
windowSize "0,24,1537,960"
|
||
viewArea "-30700,-7300,91037,67844"
|
||
cachedDiagramExtent "-7200,-11000,66000,76600"
|
||
hasePageBreakOrigin 1
|
||
pageBreakOrigin "-80000,-49000"
|
||
lastUid 751,0
|
||
defaultCommentText (CommentText
|
||
shape (Rectangle
|
||
layer 0
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65280,65280,46080"
|
||
lineColor "0,0,32768"
|
||
)
|
||
xt "0,0,15000,5000"
|
||
)
|
||
text (MLText
|
||
va (VaSet
|
||
fg "0,0,32768"
|
||
)
|
||
xt "200,200,3200,1400"
|
||
st "
|
||
Text
|
||
"
|
||
tm "CommentText"
|
||
wrapOption 3
|
||
visibleHeight 4600
|
||
visibleWidth 14600
|
||
)
|
||
)
|
||
defaultRequirementText (RequirementText
|
||
shape (ZoomableIcon
|
||
layer 0
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "59904,39936,65280"
|
||
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tm "WireNameMgr"
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sat 32
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eat 32
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tg (WTG
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tm "WireNameMgr"
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stg "VerticalLayoutStrategy"
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va (VaSet
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tm "PortMapTextMgr"
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tm "FrameTitleTextMgr"
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ps "TopLeftStrategy"
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tm "FrameSeqNumMgr"
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ps "BottomRightOffsetStrategy"
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stg "VerticalLayoutStrategy"
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*139 (MLText
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tm "BdFrameDeclTextMgr"
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title (TextAssociate
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ps "TopLeftStrategy"
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text (MLText
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va (VaSet
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tm "FrameTitleTextMgr"
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tm "FrameSeqNumMgr"
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stg "VerticalLayoutStrategy"
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va (VaSet
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*141 (MLText
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va (VaSet
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tm "BdFrameDeclTextMgr"
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style 3
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defaultSaCptPort (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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vasetType 1
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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decl (Decl
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defaultSaCptPortBuffer (CptPort
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ps "OnEdgeStrategy"
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shape (Diamond
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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thePort (LogicalPort
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m 3
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decl (Decl
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defaultDeclText (MLText
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va (VaSet
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uid 1,0
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stg "BdArchDeclBlockLS"
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uid 2,0
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va (VaSet
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portLabel (Text
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uid 3,0
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va (VaSet
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preUserLabel (Text
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uid 4,0
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va (VaSet
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uid 5,0
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va (VaSet
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tm "BdDeclarativeTextMgr"
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diagSignalLabel (Text
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uid 6,0
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va (VaSet
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font "Verdana,9,1"
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postUserLabel (Text
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uid 7,0
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va (VaSet
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postUserText (MLText
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uid 8,0
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va (VaSet
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isHidden 1
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tm "BdDeclarativeTextMgr"
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commonDM (CommonDM
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ldm (LogicalDM
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emptyRow *142 (LEmptyRow
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uid 166,0
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*144 (TitleRowHdr
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*145 (FilterRowHdr
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)
|
||
*146 (RefLabelColHdr
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||
tm "RefLabelColHdrMgr"
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)
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*147 (RowExpandColHdr
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||
tm "RowExpandColHdrMgr"
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)
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*148 (GroupColHdr
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||
tm "GroupColHdrMgr"
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)
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*149 (NameColHdr
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tm "BlockDiagramNameColHdrMgr"
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*150 (ModeColHdr
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||
tm "BlockDiagramModeColHdrMgr"
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*151 (TypeColHdr
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||
tm "BlockDiagramTypeColHdrMgr"
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)
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*152 (BoundsColHdr
|
||
tm "BlockDiagramBoundsColHdrMgr"
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)
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*153 (InitColHdr
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||
tm "BlockDiagramInitColHdrMgr"
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)
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*154 (EolColHdr
|
||
tm "BlockDiagramEolColHdrMgr"
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)
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*155 (LeafLogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "RaZ"
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o 1
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uid 107,0
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*156 (LeafLogPort
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port (LogicalPort
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lang 11
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n "clock"
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uid 109,0
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*157 (LeafLogPort
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port (LogicalPort
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uid 111,0
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*158 (LeafLogPort
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port (LogicalPort
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uid 113,0
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*159 (LeafLogPort
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port (LogicalPort
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uid 115,0
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*160 (LeafLogPort
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port (LogicalPort
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m 1
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decl (Decl
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o 6
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uid 117,0
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*161 (LeafLogPort
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suid 5,0
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uid 119,0
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*162 (LeafLogPort
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port (LogicalPort
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lang 11
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m 4
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o 8
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suid 8,0
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uid 551,0
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*163 (LeafLogPort
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m 4
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suid 9,0
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uid 553,0
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*164 (LeafLogPort
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port (LogicalPort
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lang 11
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m 4
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uid 555,0
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pdm (PhysicalDM
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uid 179,0
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sheetRow (SheetRow
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emptyMRCItem *166 (MRCItem
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litem &142
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pos 10
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uid 181,0
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optionalChildren [
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litem &143
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uid 182,0
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*168 (MRCItem
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litem &144
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pos 1
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uid 183,0
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*169 (MRCItem
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litem &145
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*170 (MRCItem
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litem &155
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*171 (MRCItem
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litem &156
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*172 (MRCItem
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litem &157
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*173 (MRCItem
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litem &158
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*174 (MRCItem
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litem &159
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pos 4
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*175 (MRCItem
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litem &160
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dimension 20
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*176 (MRCItem
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litem &161
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pos 6
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dimension 20
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uid 120,0
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)
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*177 (MRCItem
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litem &162
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pos 7
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dimension 20
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uid 552,0
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*178 (MRCItem
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litem &163
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pos 8
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*179 (MRCItem
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litem &164
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*181 (MRCItem
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litem &148
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pos 1
|
||
dimension 50
|
||
uid 187,0
|
||
)
|
||
*182 (MRCItem
|
||
litem &149
|
||
pos 2
|
||
dimension 100
|
||
uid 188,0
|
||
)
|
||
*183 (MRCItem
|
||
litem &150
|
||
pos 3
|
||
dimension 50
|
||
uid 189,0
|
||
)
|
||
*184 (MRCItem
|
||
litem &151
|
||
pos 4
|
||
dimension 100
|
||
uid 190,0
|
||
)
|
||
*185 (MRCItem
|
||
litem &152
|
||
pos 5
|
||
dimension 100
|
||
uid 191,0
|
||
)
|
||
*186 (MRCItem
|
||
litem &153
|
||
pos 6
|
||
dimension 50
|
||
uid 192,0
|
||
)
|
||
*187 (MRCItem
|
||
litem &154
|
||
pos 7
|
||
dimension 80
|
||
uid 193,0
|
||
)
|
||
]
|
||
)
|
||
fixedCol 4
|
||
fixedRow 2
|
||
name "Ports"
|
||
uid 180,0
|
||
vaOverrides [
|
||
]
|
||
)
|
||
]
|
||
)
|
||
uid 165,0
|
||
)
|
||
genericsCommonDM (CommonDM
|
||
ldm (LogicalDM
|
||
emptyRow *188 (LEmptyRow
|
||
)
|
||
uid 195,0
|
||
optionalChildren [
|
||
*189 (RefLabelRowHdr
|
||
)
|
||
*190 (TitleRowHdr
|
||
)
|
||
*191 (FilterRowHdr
|
||
)
|
||
*192 (RefLabelColHdr
|
||
tm "RefLabelColHdrMgr"
|
||
)
|
||
*193 (RowExpandColHdr
|
||
tm "RowExpandColHdrMgr"
|
||
)
|
||
*194 (GroupColHdr
|
||
tm "GroupColHdrMgr"
|
||
)
|
||
*195 (NameColHdr
|
||
tm "GenericNameColHdrMgr"
|
||
)
|
||
*196 (TypeColHdr
|
||
tm "GenericTypeColHdrMgr"
|
||
)
|
||
*197 (InitColHdr
|
||
tm "GenericValueColHdrMgr"
|
||
)
|
||
*198 (PragmaColHdr
|
||
tm "GenericPragmaColHdrMgr"
|
||
)
|
||
*199 (EolColHdr
|
||
tm "GenericEolColHdrMgr"
|
||
)
|
||
]
|
||
)
|
||
pdm (PhysicalDM
|
||
displayShortBounds 1
|
||
editShortBounds 1
|
||
uid 207,0
|
||
optionalChildren [
|
||
*200 (Sheet
|
||
sheetRow (SheetRow
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||
headerVa (MVa
|
||
cellColor "49152,49152,49152"
|
||
fontColor "0,0,0"
|
||
font "Tahoma,10,0"
|
||
)
|
||
cellVa (MVa
|
||
cellColor "65535,65535,65535"
|
||
fontColor "0,0,0"
|
||
font "Tahoma,10,0"
|
||
)
|
||
groupVa (MVa
|
||
cellColor "39936,56832,65280"
|
||
fontColor "0,0,0"
|
||
font "Tahoma,10,0"
|
||
)
|
||
emptyMRCItem *201 (MRCItem
|
||
litem &188
|
||
pos 0
|
||
dimension 20
|
||
)
|
||
uid 209,0
|
||
optionalChildren [
|
||
*202 (MRCItem
|
||
litem &189
|
||
pos 0
|
||
dimension 20
|
||
uid 210,0
|
||
)
|
||
*203 (MRCItem
|
||
litem &190
|
||
pos 1
|
||
dimension 23
|
||
uid 211,0
|
||
)
|
||
*204 (MRCItem
|
||
litem &191
|
||
pos 2
|
||
hidden 1
|
||
dimension 20
|
||
uid 212,0
|
||
)
|
||
]
|
||
)
|
||
sheetCol (SheetCol
|
||
propVa (MVa
|
||
cellColor "0,49152,49152"
|
||
fontColor "0,0,0"
|
||
font "Tahoma,10,0"
|
||
textAngle 90
|
||
)
|
||
uid 213,0
|
||
optionalChildren [
|
||
*205 (MRCItem
|
||
litem &192
|
||
pos 0
|
||
dimension 20
|
||
uid 214,0
|
||
)
|
||
*206 (MRCItem
|
||
litem &194
|
||
pos 1
|
||
dimension 50
|
||
uid 215,0
|
||
)
|
||
*207 (MRCItem
|
||
litem &195
|
||
pos 2
|
||
dimension 100
|
||
uid 216,0
|
||
)
|
||
*208 (MRCItem
|
||
litem &196
|
||
pos 3
|
||
dimension 100
|
||
uid 217,0
|
||
)
|
||
*209 (MRCItem
|
||
litem &197
|
||
pos 4
|
||
dimension 50
|
||
uid 218,0
|
||
)
|
||
*210 (MRCItem
|
||
litem &198
|
||
pos 5
|
||
dimension 50
|
||
uid 219,0
|
||
)
|
||
*211 (MRCItem
|
||
litem &199
|
||
pos 6
|
||
dimension 80
|
||
uid 220,0
|
||
)
|
||
]
|
||
)
|
||
fixedCol 3
|
||
fixedRow 2
|
||
name "Ports"
|
||
uid 208,0
|
||
vaOverrides [
|
||
]
|
||
)
|
||
]
|
||
)
|
||
uid 194,0
|
||
type 1
|
||
)
|
||
activeModelName "BlockDiag"
|
||
)
|