mirror of
https://github.com/Klagarge/Cursor.git
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1842 lines
23 KiB
Plaintext
1842 lines
23 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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|
suid 32,0
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|
usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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|
uid 109,0
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|
optionalChildren [
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|
*2 (RefLabelRowHdr
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|
)
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|
*3 (TitleRowHdr
|
|
)
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|
*4 (FilterRowHdr
|
|
)
|
|
*5 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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|
)
|
|
*6 (RowExpandColHdr
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|
tm "RowExpandColHdrMgr"
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|
)
|
|
*7 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
|
*8 (NameColHdr
|
|
tm "NameColHdrMgr"
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|
)
|
|
*9 (ModeColHdr
|
|
tm "ModeColHdrMgr"
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|
)
|
|
*10 (TypeColHdr
|
|
tm "TypeColHdrMgr"
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|
)
|
|
*11 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*12 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*13 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
*14 (LogPort
|
|
port (LogicalPort
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|
m 1
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|
decl (Decl
|
|
n "A"
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|
t "unsigned"
|
|
b "(addressBitNb-1 DOWNTO 0)"
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o 1
|
|
suid 25,0
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|
)
|
|
)
|
|
uid 458,0
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|
)
|
|
*15 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "BYTE_n"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 460,0
|
|
)
|
|
*16 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "CE"
|
|
t "std_ulogic_vector"
|
|
b "(2 DOWNTO 0)"
|
|
o 3
|
|
suid 27,0
|
|
)
|
|
)
|
|
uid 462,0
|
|
)
|
|
*17 (LogPort
|
|
port (LogicalPort
|
|
m 2
|
|
decl (Decl
|
|
n "DQ"
|
|
t "std_logic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 28,0
|
|
)
|
|
)
|
|
uid 464,0
|
|
)
|
|
*18 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "OE_n"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 29,0
|
|
)
|
|
)
|
|
uid 466,0
|
|
)
|
|
*19 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "RP_n"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 30,0
|
|
)
|
|
)
|
|
uid 468,0
|
|
)
|
|
*20 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "STS"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 31,0
|
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)
|
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)
|
|
uid 470,0
|
|
)
|
|
*21 (LogPort
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|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "WE_n"
|
|
t "std_ulogic"
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o 8
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suid 32,0
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)
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)
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|
uid 472,0
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)
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]
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)
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
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|
uid 122,0
|
|
optionalChildren [
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*22 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *23 (MRCItem
|
|
litem &1
|
|
pos 8
|
|
dimension 20
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|
)
|
|
uid 124,0
|
|
optionalChildren [
|
|
*24 (MRCItem
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|
litem &2
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pos 0
|
|
dimension 20
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|
uid 125,0
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)
|
|
*25 (MRCItem
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|
litem &3
|
|
pos 1
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|
dimension 23
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|
uid 126,0
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)
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|
*26 (MRCItem
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litem &4
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pos 2
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hidden 1
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|
dimension 20
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|
uid 127,0
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)
|
|
*27 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 459,0
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)
|
|
*28 (MRCItem
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|
litem &15
|
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pos 1
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dimension 20
|
|
uid 461,0
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|
)
|
|
*29 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 20
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|
uid 463,0
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|
)
|
|
*30 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 465,0
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)
|
|
*31 (MRCItem
|
|
litem &18
|
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pos 4
|
|
dimension 20
|
|
uid 467,0
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)
|
|
*32 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 469,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 471,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 473,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 128,0
|
|
optionalChildren [
|
|
*35 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 129,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 130,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 131,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 132,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 133,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 134,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 135,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 136,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 123,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 108,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *43 (LEmptyRow
|
|
)
|
|
uid 138,0
|
|
optionalChildren [
|
|
*44 (RefLabelRowHdr
|
|
)
|
|
*45 (TitleRowHdr
|
|
)
|
|
*46 (FilterRowHdr
|
|
)
|
|
*47 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*48 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*49 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*50 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*51 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*52 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*53 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*54 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*55 (LogGeneric
|
|
generic (GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "24"
|
|
)
|
|
uid 210,0
|
|
)
|
|
*56 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 212,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 150,0
|
|
optionalChildren [
|
|
*57 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *58 (MRCItem
|
|
litem &43
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 152,0
|
|
optionalChildren [
|
|
*59 (MRCItem
|
|
litem &44
|
|
pos 0
|
|
dimension 20
|
|
uid 153,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 23
|
|
uid 154,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 155,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
uid 211,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &56
|
|
pos 1
|
|
dimension 20
|
|
uid 213,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 156,0
|
|
optionalChildren [
|
|
*64 (MRCItem
|
|
litem &47
|
|
pos 0
|
|
dimension 20
|
|
uid 157,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 50
|
|
uid 158,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
dimension 100
|
|
uid 159,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &51
|
|
pos 3
|
|
dimension 100
|
|
uid 160,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &52
|
|
pos 4
|
|
dimension 50
|
|
uid 161,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &53
|
|
pos 5
|
|
dimension 50
|
|
uid 162,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &54
|
|
pos 6
|
|
dimension 80
|
|
uid 163,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 151,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 137,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "flash_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "memory_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory_test/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "flash_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash_tester/interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:28"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "flash_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
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