553 lines
18 KiB
C
553 lines
18 KiB
C
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/**
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******************************************************************************
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* @file stm32f7xx_hal_pwr_ex.c
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* @author MCD Application Team
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* @brief Extended PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of PWR extension peripheral:
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* + Peripheral Extended features functions
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @defgroup PWREx PWREx
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* @brief PWR HAL module driver
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup PWREx_Private_Constants
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* @{
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*/
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#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
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#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
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#define PWR_BKPREG_TIMEOUT_VALUE 1000
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#define PWR_VOSRDY_TIMEOUT_VALUE 1000
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
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* @{
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*/
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/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
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* @brief Peripheral Extended features functions
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*
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@verbatim
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===============================================================================
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##### Peripheral extended features functions #####
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===============================================================================
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*** Main and Backup Regulators configuration ***
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================================================
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[..]
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(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
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the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
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retained even in Standby or VBAT mode when the low power backup regulator
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is enabled. It can be considered as an internal EEPROM when VBAT is
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always present. You can use the HAL_PWREx_EnableBkUpReg() function to
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enable the low power backup regulator.
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(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
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the backup SRAM is powered from VDD which replaces the VBAT power supply to
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save battery life.
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(+) The backup SRAM is not mass erased by a tamper event. It is read
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protected to prevent confidential data, such as cryptographic private
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key, from being accessed. The backup SRAM can be erased only through
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the Flash interface when a protection level change from level 1 to
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level 0 is requested.
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-@- Refer to the description of Read protection (RDP) in the Flash
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programming manual.
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(+) The main internal regulator can be configured to have a tradeoff between
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performance and power consumption when the device does not operate at
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the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
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macro which configure VOS bit in PWR_CR register
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Refer to the product datasheets for more details.
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*** FLASH Power Down configuration ****
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=======================================
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[..]
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(+) By setting the FPDS bit in the PWR_CR register by using the
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HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
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down mode when the device enters Stop mode. When the Flash memory
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is in power down mode, an additional startup delay is incurred when
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waking up from Stop mode.
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*** Over-Drive and Under-Drive configuration ****
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=================================================
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[..]
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(+) In Run mode: the main regulator has 2 operating modes available:
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(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
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voltage scaling (scale 1, scale 2 or scale 3)
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(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
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higher frequency than the normal mode for a given voltage scaling (scale 1,
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scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
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disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
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the sequence described in Reference manual.
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(+) In Stop mode: the main regulator or low power regulator supplies a low power
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voltage to the 1.2V domain, thus preserving the content of registers
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and internal SRAM. 2 operating modes are available:
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(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
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available when the main regulator or the low power regulator is used in Scale 3 or
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low voltage mode.
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(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
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available when the main regulator or the low power regulator is in low voltage mode.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables the Backup Regulator.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
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{
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uint32_t tickstart = 0;
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/* Enable Backup regulator */
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PWR->CSR1 |= PWR_CSR1_BRE;
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/* Workaround for the following hardware bug: */
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/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
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PWR->CSR1 |= PWR_CSR1_EIWUP;
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till Backup regulator ready flag is set */
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while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Disables the Backup Regulator.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
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{
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uint32_t tickstart = 0;
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/* Disable Backup regulator */
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PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
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/* Workaround for the following hardware bug: */
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/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
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PWR->CSR1 |= PWR_CSR1_EIWUP;
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till Backup regulator ready flag is set */
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while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
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{
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if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Enables the Flash Power Down in Stop mode.
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* @retval None
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*/
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void HAL_PWREx_EnableFlashPowerDown(void)
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{
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/* Enable the Flash Power Down */
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PWR->CR1 |= PWR_CR1_FPDS;
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}
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/**
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* @brief Disables the Flash Power Down in Stop mode.
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* @retval None
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*/
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void HAL_PWREx_DisableFlashPowerDown(void)
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{
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/* Disable the Flash Power Down */
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PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
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}
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/**
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* @brief Enables Main Regulator low voltage mode.
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* @retval None
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*/
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void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
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{
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/* Enable Main regulator low voltage */
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PWR->CR1 |= PWR_CR1_MRUDS;
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}
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/**
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* @brief Disables Main Regulator low voltage mode.
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* @retval None
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*/
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void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
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{
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/* Disable Main regulator low voltage */
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PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
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}
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/**
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* @brief Enables Low Power Regulator low voltage mode.
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* @retval None
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*/
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void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
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{
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/* Enable low power regulator */
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PWR->CR1 |= PWR_CR1_LPUDS;
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}
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/**
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* @brief Disables Low Power Regulator low voltage mode.
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* @retval None
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*/
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void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
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{
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/* Disable low power regulator */
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PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
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}
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/**
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* @brief Activates the Over-Drive mode.
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* @note This mode allows the CPU and the core logic to operate at a higher frequency
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* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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* @note It is recommended to enter or exit Over-drive mode when the application is not running
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* critical tasks and when the system clock source is either HSI or HSE.
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* During the Over-drive switch activation, no peripheral clocks should be enabled.
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* The peripheral clocks must be enabled once the Over-drive mode is activated.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
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{
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uint32_t tickstart = 0;
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__HAL_RCC_PWR_CLK_ENABLE();
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/* Enable the Over-drive to extend the clock frequency to 216 MHz */
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__HAL_PWR_OVERDRIVE_ENABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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{
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if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Enable the Over-drive switch */
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__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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{
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if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Deactivates the Over-Drive mode.
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* @note This mode allows the CPU and the core logic to operate at a higher frequency
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* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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* @note It is recommended to enter or exit Over-drive mode when the application is not running
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* critical tasks and when the system clock source is either HSI or HSE.
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* During the Over-drive switch activation, no peripheral clocks should be enabled.
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* The peripheral clocks must be enabled once the Over-drive mode is activated.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
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{
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uint32_t tickstart = 0;
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__HAL_RCC_PWR_CLK_ENABLE();
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/* Disable the Over-drive switch */
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__HAL_PWR_OVERDRIVESWITCHING_DISABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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{
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if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Disable the Over-drive */
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__HAL_PWR_OVERDRIVE_DISABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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{
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if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Enters in Under-Drive STOP mode.
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*
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* @note This mode can be selected only when the Under-Drive is already active
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*
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* @note This mode is enabled only with STOP low power mode.
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* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
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* mode is only available when the main regulator or the low power regulator
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* is in low voltage mode
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*
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* @note If the Under-drive mode was enabled, it is automatically disabled after
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* exiting Stop mode.
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* When the voltage regulator operates in Under-drive mode, an additional
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* startup delay is induced when waking up from Stop mode.
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*
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* @note In Stop mode, all I/O pins keep the same state as in Run mode.
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*
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* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
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* the HSI RC oscillator is selected as system clock.
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*
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* @note When the voltage regulator operates in low power mode, an additional
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* startup delay is incurred when waking up from Stop mode.
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* By keeping the internal regulator ON during Stop mode, the consumption
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* is higher although the startup time is reduced.
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*
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* @param Regulator specifies the regulator state in STOP mode.
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* This parameter can be one of the following values:
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* @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
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* and Flash memory in power-down when the device is in Stop under-drive mode
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* @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
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* and Flash memory in power-down when the device is in Stop under-drive mode
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* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
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* This parameter can be one of the following values:
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* @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
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* @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
|
|
{
|
||
|
|
uint32_t tempreg = 0;
|
||
|
|
uint32_t tickstart = 0;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
|
||
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
|
|
|
||
|
|
/* Enable Power ctrl clock */
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
/* Enable the Under-drive Mode ---------------------------------------------*/
|
||
|
|
/* Clear Under-drive flag */
|
||
|
|
__HAL_PWR_CLEAR_ODRUDR_FLAG();
|
||
|
|
|
||
|
|
/* Enable the Under-drive */
|
||
|
|
__HAL_PWR_UNDERDRIVE_ENABLE();
|
||
|
|
|
||
|
|
/* Get tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
|
||
|
|
/* Wait for UnderDrive mode is ready */
|
||
|
|
while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Select the regulator state in STOP mode ---------------------------------*/
|
||
|
|
tempreg = PWR->CR1;
|
||
|
|
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
|
||
|
|
tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
|
||
|
|
|
||
|
|
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
|
||
|
|
tempreg |= Regulator;
|
||
|
|
|
||
|
|
/* Store the new value */
|
||
|
|
PWR->CR1 = tempreg;
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
|
|
|
||
|
|
/* Select STOP mode entry --------------------------------------------------*/
|
||
|
|
if(STOPEntry == PWR_SLEEPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Returns Voltage Scaling Range.
|
||
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
|
||
|
|
* PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
|
||
|
|
*/
|
||
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
||
|
|
{
|
||
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configures the main internal regulator output voltage.
|
||
|
|
* @param VoltageScaling specifies the regulator output voltage to achieve
|
||
|
|
* a tradeoff between performance and power consumption.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
|
||
|
|
* typical output voltage at 1.4 V,
|
||
|
|
* system frequency up to 216 MHz.
|
||
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
|
||
|
|
* typical output voltage at 1.2 V,
|
||
|
|
* system frequency up to 180 MHz.
|
||
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
|
||
|
|
* typical output voltage at 1.00 V,
|
||
|
|
* system frequency up to 151 MHz.
|
||
|
|
* @note To update the system clock frequency(SYSCLK):
|
||
|
|
* - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
|
||
|
|
* - Call the HAL_RCC_OscConfig() to configure the PLL.
|
||
|
|
* - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
|
||
|
|
* - Set the new system clock frequency using the HAL_RCC_ClockConfig().
|
||
|
|
* @note The scale can be modified only when the HSI or HSE clock source is selected
|
||
|
|
* as system clock source, otherwise the API returns HAL_ERROR.
|
||
|
|
* @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
|
||
|
|
* value in the PWR_CR1 register are not taken in account.
|
||
|
|
* @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
|
||
|
|
* @note The new voltage scale is active only when the PLL is ON.
|
||
|
|
* @retval HAL Status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
||
|
|
{
|
||
|
|
uint32_t tickstart = 0;
|
||
|
|
|
||
|
|
assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
|
||
|
|
|
||
|
|
/* Enable Power ctrl clock */
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
|
||
|
|
/* Check if the PLL is used as system clock or not */
|
||
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
||
|
|
{
|
||
|
|
/* Disable the main PLL */
|
||
|
|
__HAL_RCC_PLL_DISABLE();
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
/* Wait till PLL is disabled */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set Range */
|
||
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
|
||
|
|
|
||
|
|
/* Enable the main PLL */
|
||
|
|
__HAL_RCC_PLL_ENABLE();
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get Start Tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
|
||
|
|
{
|
||
|
|
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
|
||
|
|
{
|
||
|
|
return HAL_TIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
return HAL_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|