388 lines
15 KiB
C++
388 lines
15 KiB
C++
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/**
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******************************************************************************
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* File Name : STM32DMA.cpp
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under Ultimate Liberty license
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* SLA0044, the "License"; You may not use this file except in compliance with
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* the License. You may obtain a copy of the License at:
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* www.st.com/SLA0044
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*
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******************************************************************************
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*/
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#include "stm32f7xx_hal.h"
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#include "stm32f7xx_hal_dma2d.h"
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#include <STM32DMA.hpp>
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#include <cassert>
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#include <touchgfx/Color.hpp>
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#include <touchgfx/hal/HAL.hpp>
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#include <touchgfx/hal/OSWrappers.hpp>
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#include <touchgfx/lcd/LCD.hpp>
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/* Makes touchgfx specific types and variables visible to this file */
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using namespace touchgfx;
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typedef struct
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{
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const uint16_t format;
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const uint16_t size;
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const uint32_t* const data;
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} clutData_t;
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extern "C" DMA2D_HandleTypeDef hdma2d;
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extern "C" {
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static void DMA2D_XferCpltCallback(DMA2D_HandleTypeDef* handle)
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{
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(void)handle; // Unused argument
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HAL::getInstance()->signalDMAInterrupt();
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}
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}
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STM32F7DMA::STM32F7DMA()
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: DMA_Interface(dma_queue), dma_queue(queue_storage, sizeof(queue_storage) / sizeof(queue_storage[0]))
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{
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}
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STM32F7DMA::~STM32F7DMA()
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{
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/* Disable DMA2D global Interrupt */
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NVIC_DisableIRQ(DMA2D_IRQn);
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}
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void STM32F7DMA::initialize()
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{
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/* Ensure DMA2D Clock is enabled */
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__HAL_RCC_DMA2D_CLK_ENABLE();
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__HAL_RCC_DMA2D_FORCE_RESET();
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__HAL_RCC_DMA2D_RELEASE_RESET();
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/* Add transfer complete callback function */
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hdma2d.XferCpltCallback = DMA2D_XferCpltCallback;
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/* Enable DMA2D global Interrupt */
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NVIC_EnableIRQ(DMA2D_IRQn);
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}
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inline uint32_t STM32F7DMA::getChromARTInputFormat(Bitmap::BitmapFormat format)
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{
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// Default color mode set to ARGB8888
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uint32_t dma2dColorMode = DMA2D_INPUT_ARGB8888;
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switch (format)
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{
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case Bitmap::ARGB8888: /* DMA2D input mode set to 32bit ARGB */
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dma2dColorMode = DMA2D_INPUT_ARGB8888;
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break;
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case Bitmap::RGB888: /* DMA2D input mode set to 24bit RGB */
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dma2dColorMode = DMA2D_INPUT_RGB888;
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break;
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case Bitmap::RGB565: /* DMA2D input mode set to 16bit RGB */
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dma2dColorMode = DMA2D_INPUT_RGB565;
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break;
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case Bitmap::ARGB2222: /* Fall through */
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case Bitmap::ABGR2222: /* Fall through */
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case Bitmap::RGBA2222: /* Fall through */
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case Bitmap::BGRA2222: /* Fall through */
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case Bitmap::L8: /* DMA2D input mode set to 8bit Color Look up table*/
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dma2dColorMode = DMA2D_INPUT_L8;
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break;
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case Bitmap::BW: /* Fall through */
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case Bitmap::BW_RLE: /* Fall through */
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case Bitmap::GRAY4: /* Fall through */
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case Bitmap::GRAY2: /* Fall through */
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default: /* Unsupported input format for DMA2D */
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assert(0 && "Unsupported Format!");
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break;
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}
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return dma2dColorMode;
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}
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inline uint32_t STM32F7DMA::getChromARTOutputFormat(Bitmap::BitmapFormat format)
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{
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// Default color mode set to ARGB8888
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uint32_t dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
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switch (format)
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{
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case Bitmap::ARGB8888: /* DMA2D output mode set to 32bit ARGB */
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dma2dColorMode = DMA2D_OUTPUT_ARGB8888;
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break;
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case Bitmap::RGB888: /* Fall through */
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case Bitmap::ARGB2222: /* Fall through */
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case Bitmap::ABGR2222: /* Fall through */
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case Bitmap::RGBA2222: /* Fall through */
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case Bitmap::BGRA2222: /* DMA2D output mode set to 24bit RGB */
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dma2dColorMode = DMA2D_OUTPUT_RGB888;
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break;
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case Bitmap::RGB565: /* DMA2D output mode set to 16bit RGB */
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dma2dColorMode = DMA2D_OUTPUT_RGB565;
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break;
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case Bitmap::L8: /* Fall through */
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case Bitmap::BW: /* Fall through */
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case Bitmap::BW_RLE: /* Fall through */
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case Bitmap::GRAY4: /* Fall through */
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case Bitmap::GRAY2: /* Fall through */
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default: /* Unsupported output format for DMA2D */
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assert(0 && "Unsupported Format!");
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break;
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}
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return dma2dColorMode;
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}
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BlitOperations STM32F7DMA::getBlitCaps()
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{
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return static_cast<BlitOperations>(BLIT_OP_FILL
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| BLIT_OP_FILL_WITH_ALPHA
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| BLIT_OP_COPY
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| BLIT_OP_COPY_WITH_ALPHA
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| BLIT_OP_COPY_ARGB8888
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| BLIT_OP_COPY_ARGB8888_WITH_ALPHA
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| BLIT_OP_COPY_A4
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| BLIT_OP_COPY_A8);
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}
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/*
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* void STM32F7DMA::setupDataCopy(const BlitOp& blitOp) handles blit operation of
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* BLIT_OP_COPY
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* BLIT_OP_COPY_WITH_ALPHA
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* BLIT_OP_COPY_ARGB8888
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* BLIT_OP_COPY_ARGB8888_WITH_ALPHA
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* BLIT_OP_COPY_A4
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* BLIT_OP_COPY_A8
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*/
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void STM32F7DMA::setupDataCopy(const BlitOp& blitOp)
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{
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uint32_t dma2dForegroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.srcFormat));
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uint32_t dma2dBackgroundColorMode = getChromARTInputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
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uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
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/* DMA2D OOR register configuration ------------------------------------------*/
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WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* DMA2D BGOR register configuration -------------------------------------*/
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WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
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/* DMA2D FGOR register configuration -------------------------------------*/
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WRITE_REG(DMA2D->FGOR, blitOp.srcLoopStride - blitOp.nSteps);
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/* DMA2D OPFCCR register configuration ---------------------------------------*/
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WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
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/* Configure DMA2D data size */
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WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
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/* Configure DMA2D destination address */
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WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Configure DMA2D source address */
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WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pSrc));
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switch (blitOp.operation)
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{
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case BLIT_OP_COPY_A4:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A4 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* set DMA2D foreground color */
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WRITE_REG(DMA2D->FGCOLR, ((blitOp.color & 0xF800) << 8) | ((blitOp.color & 0x07E0) << 5) | ((blitOp.color & 0x001F) << 3));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_A8:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, DMA2D_INPUT_A8 | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* set DMA2D foreground color */
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WRITE_REG(DMA2D->FGCOLR, ((blitOp.color & 0xF800) << 8) | ((blitOp.color & 0x07E0) << 5) | ((blitOp.color & 0x001F) << 3));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_WITH_ALPHA:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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if (blitOp.srcFormat == Bitmap::L8)
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{
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const clutData_t* const palette = reinterpret_cast<const clutData_t*>(blitOp.pClut);
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/* Write foreground CLUT memory address */
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WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&palette->data));
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switch ((Bitmap::ClutFormat)palette->format)
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{
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case Bitmap::CLUT_FORMAT_L8_ARGB8888:
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/* Write foreground CLUT size and CLUT color mode */
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MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_ARGB8888 << DMA2D_FGPFCCR_CCM_Pos)));
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break;
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case Bitmap::CLUT_FORMAT_L8_RGB888:
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MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
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break;
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case Bitmap::CLUT_FORMAT_L8_RGB565:
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default:
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assert(0 && "Unsupported format");
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break;
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}
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/* Enable the CLUT loading for the foreground */
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SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
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while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U)
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{
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__NOP();
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}
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DMA2D->IFCR = (DMA2D_FLAG_CTC);
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}
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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case BLIT_OP_COPY_ARGB8888:
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case BLIT_OP_COPY_ARGB8888_WITH_ALPHA:
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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/* Write DMA2D BGPFCCR register */
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WRITE_REG(DMA2D->BGPFCCR, dma2dBackgroundColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
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/* Configure DMA2D Stream source2 address */
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WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
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/* Set DMA2D mode */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_BLEND | DMA2D_IT_TC | DMA2D_CR_START);
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break;
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default: /* BLIT_OP_COPY */
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/* Set DMA2D color mode and alpha mode */
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WRITE_REG(DMA2D->FGPFCCR, dma2dForegroundColorMode | (DMA2D_COMBINE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | (blitOp.alpha << 24));
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if (blitOp.srcFormat == Bitmap::L8)
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{
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const clutData_t* const palette = reinterpret_cast<const clutData_t*>(blitOp.pClut);
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/* Write foreground CLUT memory address */
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WRITE_REG(DMA2D->FGCMAR, reinterpret_cast<uint32_t>(&palette->data));
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/* Write foreground CLUT size and CLUT color mode */
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MODIFY_REG(DMA2D->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), (((palette->size - 1) << DMA2D_FGPFCCR_CS_Pos) | (DMA2D_CCM_RGB888 << DMA2D_FGPFCCR_CCM_Pos)));
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/* Enable the CLUT loading for the foreground */
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SET_BIT(DMA2D->FGPFCCR, DMA2D_FGPFCCR_START);
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while ((READ_REG(DMA2D->FGPFCCR) & DMA2D_FGPFCCR_START) != 0U)
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{
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__NOP();
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}
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DMA2D->IFCR = (DMA2D_FLAG_CTC);
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/* Start DMA2D */
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WRITE_REG(DMA2D->CR, DMA2D_M2M_PFC | DMA2D_IT_TC | DMA2D_CR_START);
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}
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else
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{
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/* Start DMA2D */
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WRITE_REG(DMA2D->CR, DMA2D_M2M | DMA2D_IT_TC | DMA2D_CR_START);
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}
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break;
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}
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}
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/*
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* void STM32F7DMA::setupDataFill(const BlitOp& blitOp) handles blit operation of
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* BLIT_OP_FILL
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* BLIT_OP_FILL_WITH_ALPHA
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*/
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void STM32F7DMA::setupDataFill(const BlitOp& blitOp)
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|
{
|
||
|
|
uint32_t dma2dOutputColorMode = getChromARTOutputFormat(static_cast<Bitmap::BitmapFormat>(blitOp.dstFormat));
|
||
|
|
|
||
|
|
/* DMA2D OPFCCR register configuration ---------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->OPFCCR, dma2dOutputColorMode);
|
||
|
|
|
||
|
|
/* Configure DMA2D data size */
|
||
|
|
WRITE_REG(DMA2D->NLR, (blitOp.nLoops | (blitOp.nSteps << DMA2D_NLR_PL_Pos)));
|
||
|
|
|
||
|
|
/* Configure DMA2D destination address */
|
||
|
|
WRITE_REG(DMA2D->OMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
|
||
|
|
|
||
|
|
/* DMA2D OOR register configuration ------------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->OOR, blitOp.dstLoopStride - blitOp.nSteps);
|
||
|
|
|
||
|
|
if (blitOp.operation == BLIT_OP_FILL_WITH_ALPHA)
|
||
|
|
{
|
||
|
|
/* DMA2D BGOR register configuration -------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->BGOR, blitOp.dstLoopStride - blitOp.nSteps);
|
||
|
|
|
||
|
|
/* DMA2D FGOR register configuration -------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->FGOR, blitOp.dstLoopStride - blitOp.nSteps);
|
||
|
|
|
||
|
|
/* Write DMA2D BGPFCCR register */
|
||
|
|
WRITE_REG(DMA2D->BGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
|
||
|
|
|
||
|
|
/* Write DMA2D FGPFCCR register */
|
||
|
|
WRITE_REG(DMA2D->FGPFCCR, CM_A8 | (DMA2D_REPLACE_ALPHA << DMA2D_BGPFCCR_AM_Pos) | ((blitOp.alpha << 24) & DMA2D_BGPFCCR_ALPHA));
|
||
|
|
|
||
|
|
/* DMA2D FGCOLR register configuration -------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->FGCOLR, ((blitOp.alpha << 24) | ((blitOp.color & 0xF800) << 8) | ((blitOp.color & 0x07E0) << 5) | ((blitOp.color & 0x001F) << 3)) & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED));
|
||
|
|
|
||
|
|
/* Configure DMA2D Stream source2 address */
|
||
|
|
WRITE_REG(DMA2D->BGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
|
||
|
|
|
||
|
|
/* Configure DMA2D source address */
|
||
|
|
WRITE_REG(DMA2D->FGMAR, reinterpret_cast<uint32_t>(blitOp.pDst));
|
||
|
|
|
||
|
|
/* Enable the Peripheral and Enable the transfer complete interrupt */
|
||
|
|
WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_M2M_BLEND));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Write DMA2D FGPFCCR register */
|
||
|
|
WRITE_REG(DMA2D->FGPFCCR, dma2dOutputColorMode | (DMA2D_NO_MODIF_ALPHA << DMA2D_BGPFCCR_AM_Pos));
|
||
|
|
|
||
|
|
/* DMA2D FGOR register configuration -------------------------------------*/
|
||
|
|
WRITE_REG(DMA2D->FGOR, 0);
|
||
|
|
|
||
|
|
if (blitOp.dstFormat == Bitmap::RGB565)
|
||
|
|
{
|
||
|
|
// set color
|
||
|
|
WRITE_REG(DMA2D->OCOLR, blitOp.color);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
// set color
|
||
|
|
WRITE_REG(DMA2D->OCOLR, (blitOp.alpha << 24) | (blitOp.alpha << 24) | ((blitOp.color & 0xF800) << 8) | ((blitOp.color & 0x07E0) << 5) | ((blitOp.color & 0x001F) << 3));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the Peripheral and Enable the transfer complete interrupt */
|
||
|
|
WRITE_REG(DMA2D->CR, (DMA2D_IT_TC | DMA2D_CR_START | DMA2D_R2M));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|