40 lines
1.2 KiB
VHDL
40 lines
1.2 KiB
VHDL
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USE std.textio.all;
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ARCHITECTURE rtl OF bramBinASCIIInit IS
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-- Define ramContent type
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type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0);
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-- Define function to create initvalue signal
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impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is
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FILE ramContentFile : text is in ramContentFilenAme;
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variable ramContentFileLine : line;
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variable ramContent : ramContentType;
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begin
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for i in ramContentType'range loop
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readline(ramContentFile, ramContentFileLine);
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read(ramContentFileLine, ramContent(i));
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end loop;
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return ramContent;
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end function;
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-- Declare ramContent signal
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shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile);
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BEGIN
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-- Port A
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process(clock)
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begin
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if clock'event and clock='1' then
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if en = '1' then
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if writeEn = '1' then
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dataOut <= dataIn;
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ramContent(to_integer(unsigned(addressIn))) := to_bitvector(dataIn,'0');
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else
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dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn))));
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end if;
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end if;
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end if;
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end process;
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END ARCHITECTURE rtl;
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