15 lines
287 B
VHDL
15 lines
287 B
VHDL
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ARCHITECTURE RTL OF sdramControllerStoreData IS
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BEGIN
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storeData : process(reset, clock)
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begin
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if reset = '1' then
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memDataOut <= (others => '0');
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elsif rising_edge(clock) then
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memDataOut <= ramDataOut;
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end if;
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end process storeData;
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END ARCHITECTURE RTL;
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