93 lines
3.6 KiB
VHDL
93 lines
3.6 KiB
VHDL
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE test OF uvmRs232_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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-- RS232 speed
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constant rs232Period: time := (1.0/rs232BaudRate) * 1 sec;
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-- RS232 Rx
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signal rs232RxChar : character := ' ';
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-- RS232 Tx
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signal rs232TxString : string(1 to 32);
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signal rs232SendString: std_uLogic;
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signal rs232SendDone: std_uLogic;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- Tx sequence
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txSequence : process
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begin
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rs232SendString <= '0';
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rs232TxString <= (others => ' ');
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wait for 500 us;
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-- send 'Hi'
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rs232TxString <= pad("Hi", rs232TxString'length);
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rs232SendString <= '1', '0' after 1 ns;
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wait until rs232SendDone = '1';
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-- end of transmission
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wait;
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end process txSequence;
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--============================================================================
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-- RS232 Rx
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storeRxByte: process(clock_int)
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begin
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if rising_edge(clock_int) then
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if dataValid = '1' then
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rs232RxChar <= character'val(to_integer(unsigned(dataOut)));
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end if;
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end if;
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end process storeRxByte;
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------------------------------------------------------------------------------
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-- RS232 Tx
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rsSendString: process
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constant rs232CharPeriod : time := 15*rs232Period;
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variable outStringRight: natural;
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variable outchar: character;
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begin
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-- wait for command
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send <= '0';
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dataIn <= (others => '0');
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rs232SendDone <= '0';
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wait until rising_edge(rs232SendString);
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-- find string length
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outStringRight := rs232TxString'right;
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while rs232TxString(outStringRight) = ' ' loop
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outStringRight := outStringRight-1;
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end loop;
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-- send characters
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for index in rs232TxString'left to outStringRight loop
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outchar := rs232TxString(index);
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dataIn <= std_ulogic_vector(to_unsigned(
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character'pos(outchar), dataIn'length
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));
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wait until rising_edge(clock_int);
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send <= '1', '0' after clockPeriod;
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wait for rs232CharPeriod;
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end loop;
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-- send carriage return
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outchar := cr;
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dataIn <= std_ulogic_vector(to_unsigned(
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character'pos(outchar), dataIn'length
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));
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wait until rising_edge(clock_int);
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send <= '1', '0' after clockPeriod;
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wait for rs232CharPeriod;
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-- signal end of sending
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rs232SendDone <= '1';
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wait for 1 ns;
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end process rsSendString;
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END ARCHITECTURE test;
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