SEm-Labos/Libs/RS232_test/hds/serial@port@f@i@f@o_tester/interface

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value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
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value "<TBD>"
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value "C:\\EDA\\Modelsim\\win32"
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value "francois"
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variable "version"
value "2018.1 (Build 12)"
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variable "view"
value "interface"
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variable "year"
value "2019"
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(vvPair
variable "yy"
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ro 270
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xt "60550,7000,61450,9000"
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blo "61250,7000"
tm "CptPortNameMgr"
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uid 375,0
va (VaSet
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xt "44000,8300,59500,9200"
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)
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suid 26,0
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)
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tg (CPTG
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ro 270
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xt "24550,7000,25450,8500"
st "TxD"
ju 2
blo "25250,7000"
tm "CptPortNameMgr"
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)
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uid 380,0
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)
xt "44000,2000,59500,2900"
st "TxD     : IN     std_ulogic  ;
"
)
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decl (Decl
n "TxD"
t "std_ulogic"
o 2
suid 27,0
)
)
)
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ps "OnEdgeStrategy"
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va (VaSet
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xt "56625,5250,57375,6000"
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tg (CPTG
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ro 270
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xt "56550,7000,57450,10000"
st "txData"
ju 2
blo "57250,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 385,0
va (VaSet
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)
xt "44000,9200,74000,10100"
st "txData  : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "txData"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 28,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 180
va (VaSet
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xt "54625,5250,55375,6000"
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tg (CPTG
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stg "RightVerticalLayoutStrategy"
f (Text
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ro 270
va (VaSet
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xt "54550,7000,55450,10000"
st "txFull"
ju 2
blo "55250,7000"
tm "CptPortNameMgr"
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)
dt (MLText
uid 390,0
va (VaSet
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)
xt "44000,4700,59500,5600"
st "txFull  : IN     std_ulogic  ;
"
)
thePort (LogicalPort
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n "txFull"
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o 9
suid 29,0
)
)
)
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ps "OnEdgeStrategy"
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