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SEm-Labos/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd

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VHDL
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ARCHITECTURE studentVersion OF lowpass IS
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signal accumulator: unsigned((signalBitNb-1)+shiftBitNb downto 0);
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BEGIN
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process(clock)
begin
if reset = '1' then
accumulator <= (others => '0');
elsif rising_edge(clock) then
accumulator <= accumulator + resize(lowpassIn,signalBitNb+shiftBitNb) - shift_right(accumulator, shiftBitNb);
end if;
end process;
lowpassOut <= resize(shift_right(accumulator, shiftBitNb), signalBitNb);
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END ARCHITECTURE studentVersion;