34 lines
1.0 KiB
Plaintext
34 lines
1.0 KiB
Plaintext
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-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:20 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorCoefficients IS
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GENERIC(
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bitNb : positive := 16;
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coeffBitNb : positive := 16
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);
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PORT(
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sample1 : IN signed (bitNb-1 DOWNTO 0);
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sample2 : IN signed (bitNb-1 DOWNTO 0);
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sample3 : IN signed (bitNb-1 DOWNTO 0);
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sample4 : IN signed (bitNb-1 DOWNTO 0);
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a : OUT signed (coeffBitNb-1 DOWNTO 0);
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b : OUT signed (coeffBitNb-1 DOWNTO 0);
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c : OUT signed (coeffBitNb-1 DOWNTO 0);
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d : OUT signed (coeffBitNb-1 DOWNTO 0);
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interpolateLinear : IN std_ulogic
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);
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-- Declarations
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END interpolatorCoefficients ;
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