331 lines
12 KiB
VHDL
331 lines
12 KiB
VHDL
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE test OF ahbUart_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal reset_int: std_uLogic;
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-- test information
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signal noteTopSeparator : string(1 to 80) := (others => '-');
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signal errorTopSeparator : string(1 to 80) := (others => '#');
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signal bottomSeparator : string(1 to 80) := (others => '.');
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signal indentation : string(1 to 2) := (others => ' ');
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signal noteInformation : string(1 to 9) := (others => ' ');
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signal errorInformation : string(1 to 10) := (others => ' ');
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signal failureInformation : string(1 to 12) := (others => ' ');
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signal testInformation : string(1 to 50) := (others => ' ');
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-- register definition
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constant dataRegisterAddress: natural := 0;
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constant controlRegisterAddress: natural := 1;
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constant scalerRegisterAddress: natural := 2;
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constant statusRegisterAddress: natural := 1;
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constant statusValidAddress: natural := 0;
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constant valueRegisterAddress: natural := 1;
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-- AMBA bus access
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signal registerAddress: natural;
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signal registerData: integer;
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signal registerWrite: std_uLogic;
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signal registerRead: std_uLogic;
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signal writeFlag, readFlag, readFlag1: std_uLogic;
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signal writeData, readData: integer;
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-- UART access
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constant baudPeriodNb: positive := 4;
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signal uartData: integer;
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signal uartSend: std_uLogic;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset_int <= '1', '0' after 2*clockPeriod;
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hReset_n <= not(reset_int);
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clock_int <= not clock_int after clockPeriod/2;
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hClk <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- test sequence
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testSequence: process
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begin
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registerAddress <= 0;
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registerData <= 0;
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registerWrite <= '0';
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registerRead <= '0';
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uartSend <= '0';
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wait for 1 us;
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-- write baud rate
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testInformation <= pad("Writing baud rate", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= scalerRegisterAddress;
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registerData <= baudPeriodNb;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- write Tx data 55h
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testInformation <= pad("Writing Tx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerData <= 16#55#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 20*baudPeriodNb*clockPeriod;
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-- write Tx data 0Fh
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Writing Tx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerData <= 16#0F#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#02#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status sending flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 12*baudPeriodNb*clockPeriod;
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-- read status
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#00#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected no flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 20*baudPeriodNb*clockPeriod;
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-- receive AAh
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testInformation <= pad("Receiving Rx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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uartData <= 16#AA#;
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uartSend <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#04#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status receiving flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 10*baudPeriodNb*clockPeriod;
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-- read status again
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#01#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status data available flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- read data
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testInformation <= pad("Reading data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#AA#
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report
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errorTopSeparator & cr &
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errorInformation & indentation & "read data not as expected" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#00#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected no flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- end of simulation
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wait for 100 ns;
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testInformation <= pad("End of tests", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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failureInformation & indentation & testInformation & cr &
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failureInformation & bottomSeparator
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severity failure;
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wait;
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end process testSequence;
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------------------------------------------------------------------------------
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-- AMBA bus access
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-- phase 1: address and controls
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busAccess1: process
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variable writeAccess: boolean := false;
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begin
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wait on reset_int, registerWrite, registerRead;
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if falling_edge(reset_int) then
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hAddr <= (others => '-');
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hTrans <= transIdle;
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hSel <= '0';
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writeFlag <= '0';
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end if;
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if rising_edge(registerWrite) or rising_edge(registerRead) then
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writeAccess := false;
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if rising_edge(registerWrite) then
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writeAccess := true;
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end if;
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wait until rising_edge(clock_int);
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hAddr <= to_unsigned(registerAddress, hAddr'length),
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(others => '-') after clockPeriod + 1 ns;
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hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns;
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hSel <= '1', '0' after clockPeriod + 1 ns;
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if writeAccess then
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writeFlag <= '1', '0' after clockPeriod + 1 ns;
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writeData <= registerData;
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else
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readFlag <= '1', '0' after clockPeriod + 1 ns;
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end if;
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end if;
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end process busAccess1;
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hWrite <= writeFlag;
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-- phase 2: data write
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busAccess2: process
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begin
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wait until rising_edge(clock_int);
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hWData <= (others => '-');
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readFlag1 <= '0';
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if writeFlag = '1' then
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hWData <= std_uLogic_vector(to_signed(writeData, hWData'length));
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end if;
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readFlag1 <= readFlag;
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end process busAccess2;
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-- phase 3: data read
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busAccess3: process
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begin
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wait until rising_edge(clock_int);
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if readFlag1 = '1' then
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readData <= to_integer(to_01(unsigned(hRData)));
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end if;
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end process busAccess3;
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------------------------------------------------------------------------------
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-- UART access
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sendByte: process
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variable serialData: unsigned(7 downto 0);
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begin
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-- send stop bit
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RxD <= '1';
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-- get new word
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wait until rising_edge(uartSend);
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serialData := to_unsigned(uartData, serialData'length);
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-- send start bit
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RxD <= '0';
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wait for baudPeriodNb * clockPeriod;
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-- send data bits
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for index in serialData'reverse_range loop
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RxD <= serialData(index);
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wait for baudPeriodNb * clockPeriod;
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end loop;
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end process sendByte;
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END ARCHITECTURE test;
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