20 lines
672 B
VHDL
20 lines
672 B
VHDL
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ARCHITECTURE test OF sineGen_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal sClock: std_uLogic := '1';
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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reset <= '1', '0' after 2*clockPeriod;
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------------------------------------------------------------------------------
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-- controls
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step <= to_unsigned(1, step'length);
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END ARCHITECTURE test;
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