SEm-Labos/06-07-08-09-SystemOnChip/SystemOnChip/hds/beamer@soc/struct.bd

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stg "VerticalLayoutStrategy"
f (Text
uid 16737,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,-7700,95800,-6300"
st "pReadStrobe"
blo "86000,-6500"
)
)
thePort (LogicalPort
decl (Decl
n "pReadStrobe"
t "std_uLogic"
o 7
)
)
)
*24 (CptPort
uid 16738,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16739,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84250,-5375,85000,-4625"
)
tg (CPTG
uid 16740,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16741,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,-5700,96000,-4300"
st "pWriteStrobe"
blo "86000,-4500"
)
)
thePort (LogicalPort
decl (Decl
n "pWriteStrobe"
t "std_uLogic"
o 9
)
)
)
*25 (CptPort
uid 16742,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16743,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84250,-13375,85000,-12625"
)
tg (CPTG
uid 16744,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16745,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,-13700,92700,-12300"
st "pAddress"
blo "86000,-12500"
)
)
thePort (LogicalPort
decl (Decl
n "pAddress"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 2
)
)
)
*26 (CptPort
uid 16746,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16747,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84250,-11375,85000,-10625"
)
tg (CPTG
uid 16748,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16749,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,-11700,92900,-10300"
st "pDataOut"
blo "86000,-10500"
)
)
thePort (LogicalPort
decl (Decl
n "pDataOut"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 3
)
)
)
*27 (CptPort
uid 16750,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16751,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84250,-9375,85000,-8625"
)
tg (CPTG
uid 16752,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16753,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,-9700,91900,-8300"
st "pDataIn"
blo "86000,-8500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "pDataIn"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 10
)
)
)
*28 (CptPort
uid 16754,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16755,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-13375,101750,-12625"
)
tg (CPTG
uid 16756,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16757,0
va (VaSet
font "Verdana,12,0"
)
xt "95500,-13700,100000,-12300"
st "hAddr"
ju 2
blo "100000,-12500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 11
)
)
)
*29 (CptPort
uid 16758,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16759,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-11375,101750,-10625"
)
tg (CPTG
uid 16760,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16761,0
va (VaSet
font "Verdana,12,0"
)
xt "94100,-11700,100000,-10300"
st "hWData"
ju 2
blo "100000,-10500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 19
)
)
)
*30 (CptPort
uid 16762,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16763,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,2625,101750,3375"
)
tg (CPTG
uid 16764,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16765,0
va (VaSet
font "Verdana,12,0"
)
xt "94600,2300,100000,3700"
st "hRData"
ju 2
blo "100000,3500"
)
)
thePort (LogicalPort
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 4
)
)
)
*31 (CptPort
uid 16766,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16767,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-7375,101750,-6625"
)
tg (CPTG
uid 16768,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16769,0
va (VaSet
font "Verdana,12,0"
)
xt "95000,-7700,100000,-6300"
st "hWrite"
ju 2
blo "100000,-6500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hWrite"
t "std_uLogic"
o 20
)
)
)
*32 (CptPort
uid 16770,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16771,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-5375,101750,-4625"
)
tg (CPTG
uid 16772,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16773,0
va (VaSet
font "Verdana,12,0"
)
xt "95800,-5700,100000,-4300"
st "hSize"
ju 2
blo "100000,-4500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hSize"
t "std_ulogic_vector"
b "(ahbSizeBitNb-1 DOWNTO 0)"
o 17
)
)
)
*33 (CptPort
uid 16774,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16775,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-3375,101750,-2625"
)
tg (CPTG
uid 16776,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16777,0
va (VaSet
font "Verdana,12,0"
)
xt "95100,-3700,100000,-2300"
st "hBurst"
ju 2
blo "100000,-2500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hBurst"
t "std_ulogic_vector"
b "(ahbBurstBitNb-1 DOWNTO 0)"
o 12
)
)
)
*34 (CptPort
uid 16778,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16779,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-1375,101750,-625"
)
tg (CPTG
uid 16780,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16781,0
va (VaSet
font "Verdana,12,0"
)
xt "95800,-1700,100000,-300"
st "hProt"
ju 2
blo "100000,-500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hProt"
t "std_ulogic_vector"
b "(ahbProtBitNb-1 DOWNTO 0)"
o 15
)
)
)
*35 (CptPort
uid 16782,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16783,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,-9375,101750,-8625"
)
tg (CPTG
uid 16784,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16785,0
va (VaSet
font "Verdana,12,0"
)
xt "94900,-9700,100000,-8300"
st "hTrans"
ju 2
blo "100000,-8500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 18
)
)
)
*36 (CptPort
uid 16786,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16787,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,625,101750,1375"
)
tg (CPTG
uid 16788,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16789,0
va (VaSet
font "Verdana,12,0"
)
xt "92600,300,100000,1700"
st "hMastLock"
ju 2
blo "100000,1500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hMastLock"
t "std_uLogic"
o 14
)
)
)
*37 (CptPort
uid 16790,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16791,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,4625,101750,5375"
)
tg (CPTG
uid 16792,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16793,0
va (VaSet
font "Verdana,12,0"
)
xt "94500,4300,100000,5700"
st "hReady"
ju 2
blo "100000,5500"
)
)
thePort (LogicalPort
decl (Decl
n "hReady"
t "std_uLogic"
o 5
)
)
)
*38 (CptPort
uid 16794,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16795,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,6625,101750,7375"
)
tg (CPTG
uid 16796,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16797,0
va (VaSet
font "Verdana,12,0"
)
xt "95300,6300,100000,7700"
st "hResp"
ju 2
blo "100000,7500"
)
)
thePort (LogicalPort
decl (Decl
n "hResp"
t "std_uLogic"
o 6
)
)
)
*39 (CptPort
uid 16798,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16799,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,8625,101750,9375"
)
tg (CPTG
uid 16800,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16801,0
va (VaSet
font "Verdana,12,0"
)
xt "96500,8300,100000,9700"
st "hClk"
ju 2
blo "100000,9500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hClk"
t "std_uLogic"
o 13
)
)
)
*40 (CptPort
uid 16802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16803,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "101000,10625,101750,11375"
)
tg (CPTG
uid 16804,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16805,0
va (VaSet
font "Verdana,12,0"
)
xt "93200,10300,100000,11700"
st "hReset_n"
ju 2
blo "100000,11500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReset_n"
t "std_uLogic"
o 16
)
)
)
]
shape (Rectangle
uid 16718,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "85000,-17000,101000,13000"
)
oxt "47000,12000,63000,42000"
ttg (MlTextGroup
uid 16719,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*41 (Text
uid 16720,0
va (VaSet
)
xt "85100,12700,89700,13900"
st "AhbLite"
blo "85100,13700"
tm "BdLibraryNameMgr"
)
*42 (Text
uid 16721,0
va (VaSet
)
xt "85100,13700,96400,14900"
st "ahbMasterInterface"
blo "85100,14700"
tm "CptNameMgr"
)
*43 (Text
uid 16722,0
va (VaSet
)
xt "85100,14700,88800,15900"
st "I_mst"
blo "85100,15700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16723,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16724,0
text (MLText
uid 16725,0
va (VaSet
)
xt "85000,15400,85000,15400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*44 (SaComponent
uid 16806,0
optionalChildren [
*45 (CptPort
uid 16815,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16816,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "141000,22625,141750,23375"
)
tg (CPTG
uid 16817,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16818,0
va (VaSet
font "Verdana,12,0"
)
xt "136500,22300,140000,23700"
st "hSel"
ju 2
blo "140000,23500"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_ulogic_vector"
b "( 1 TO ahbSlaveNb )"
o 5
)
)
)
*46 (CptPort
uid 16819,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16820,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "141000,26625,141750,27375"
)
tg (CPTG
uid 16821,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16822,0
va (VaSet
font "Verdana,12,0"
)
xt "133800,26300,140000,27700"
st "hRDataV"
ju 2
blo "140000,27500"
)
)
thePort (LogicalPort
decl (Decl
n "hRDataV"
t "ahbDataVector"
o 1
)
)
)
*47 (CptPort
uid 16823,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16824,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124250,28625,125000,29375"
)
tg (CPTG
uid 16825,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16826,0
va (VaSet
font "Verdana,12,0"
)
xt "126000,28300,131500,29700"
st "hReady"
blo "126000,29500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_uLogic"
o 7
)
)
)
*48 (CptPort
uid 16827,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16828,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124250,30625,125000,31375"
)
tg (CPTG
uid 16829,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16830,0
va (VaSet
font "Verdana,12,0"
)
xt "126000,30300,130700,31700"
st "hResp"
blo "126000,31500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_uLogic"
o 3
)
)
)
*49 (CptPort
uid 16831,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16832,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124250,26625,125000,27375"
)
tg (CPTG
uid 16833,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16834,0
va (VaSet
font "Verdana,12,0"
)
xt "126000,26300,131400,27700"
st "hRData"
blo "126000,27500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
)
)
)
*50 (CptPort
uid 16835,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16836,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "141000,28625,141750,29375"
)
tg (CPTG
uid 16837,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16838,0
va (VaSet
font "Verdana,12,0"
)
xt "133700,28300,140000,29700"
st "hReadyV"
ju 2
blo "140000,29500"
)
)
thePort (LogicalPort
decl (Decl
n "hReadyV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 2
)
)
)
*51 (CptPort
uid 16839,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16840,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "141000,30625,141750,31375"
)
tg (CPTG
uid 16841,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16842,0
va (VaSet
font "Verdana,12,0"
)
xt "134500,30300,140000,31700"
st "hRespV"
ju 2
blo "140000,31500"
)
)
thePort (LogicalPort
decl (Decl
n "hRespV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 4
)
)
)
]
shape (Rectangle
uid 16807,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "125000,19000,141000,35000"
)
oxt "40000,9000,56000,25000"
ttg (MlTextGroup
uid 16808,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*52 (Text
uid 16809,0
va (VaSet
)
xt "125100,34700,129700,35900"
st "AhbLite"
blo "125100,35700"
tm "BdLibraryNameMgr"
)
*53 (Text
uid 16810,0
va (VaSet
)
xt "125100,35700,133900,36900"
st "ahbMultiplexor"
blo "125100,36700"
tm "CptNameMgr"
)
*54 (Text
uid 16811,0
va (VaSet
)
xt "125100,36700,129000,37900"
st "I_mux"
blo "125100,37700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16812,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16813,0
text (MLText
uid 16814,0
va (VaSet
)
xt "125000,37400,125000,37400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*55 (SaComponent
uid 16843,0
optionalChildren [
*56 (CptPort
uid 16852,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16853,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124250,-1375,125000,-625"
)
tg (CPTG
uid 16854,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16855,0
va (VaSet
font "Verdana,12,0"
)
xt "126000,-1700,130500,-300"
st "hAddr"
blo "126000,-500"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 1
)
)
)
*57 (CptPort
uid 16856,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16857,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "141000,-1375,141750,-625"
)
tg (CPTG
uid 16858,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16859,0
va (VaSet
font "Verdana,12,0"
)
xt "136500,-1700,140000,-300"
st "hSel"
ju 2
blo "140000,-500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hSel"
t "std_ulogic_vector"
b "(1 to ahbSlaveNb)"
o 2
)
)
)
]
shape (Rectangle
uid 16844,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "125000,-5000,141000,3000"
)
oxt "39000,14000,55000,22000"
ttg (MlTextGroup
uid 16845,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*58 (Text
uid 16846,0
va (VaSet
)
xt "125100,2700,129700,3900"
st "AhbLite"
blo "125100,3700"
tm "BdLibraryNameMgr"
)
*59 (Text
uid 16847,0
va (VaSet
)
xt "125100,3700,132500,4900"
st "ahbDecoder"
blo "125100,4700"
tm "CptNameMgr"
)
*60 (Text
uid 16848,0
va (VaSet
)
xt "125100,4700,128700,5900"
st "I_dec"
blo "125100,5700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16849,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16850,0
text (MLText
uid 16851,0
va (VaSet
)
xt "125000,5400,166000,6600"
st "ahbMemoryLocation = ahbMemoryLocation    ( ahbMemoryLocationVector )  "
)
header ""
)
elements [
(GiElement
name "ahbMemoryLocation"
type "ahbMemoryLocationVector"
value "ahbMemoryLocation"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*61 (SaComponent
uid 16860,0
optionalChildren [
*62 (CptPort
uid 16869,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16870,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,-1375,157000,-625"
)
tg (CPTG
uid 16871,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16872,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,-1700,162300,-300"
st "hSelV"
blo "158000,-500"
)
)
thePort (LogicalPort
decl (Decl
n "hSelV"
t "std_ulogic_vector"
b "( 1 TO ahbSlaveNb )"
o 5
)
)
)
*63 (CptPort
uid 16873,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16874,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,625,157000,1375"
)
tg (CPTG
uid 16875,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16876,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,300,164200,1700"
st "hRDataV"
blo "158000,1500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRDataV"
t "ahbDataVector"
o 1
)
)
)
*64 (CptPort
uid 16877,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16878,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,2625,173750,3375"
)
tg (CPTG
uid 16879,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16880,0
va (VaSet
font "Verdana,12,0"
)
xt "166500,2300,172000,3700"
st "hReady"
ju 2
blo "172000,3500"
)
)
thePort (LogicalPort
decl (Decl
n "hReady"
t "std_uLogic"
o 7
)
)
)
*65 (CptPort
uid 16881,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16882,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,4625,173750,5375"
)
tg (CPTG
uid 16883,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16884,0
va (VaSet
font "Verdana,12,0"
)
xt "167300,4300,172000,5700"
st "hResp"
ju 2
blo "172000,5500"
)
)
thePort (LogicalPort
decl (Decl
n "hResp"
t "std_uLogic"
o 3
)
)
)
*66 (CptPort
uid 16885,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16886,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,625,173750,1375"
)
tg (CPTG
uid 16887,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16888,0
va (VaSet
font "Verdana,12,0"
)
xt "166600,300,172000,1700"
st "hRData"
ju 2
blo "172000,1500"
)
)
thePort (LogicalPort
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
)
)
)
*67 (CptPort
uid 16889,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16890,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,2625,157000,3375"
)
tg (CPTG
uid 16891,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16892,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,2300,164300,3700"
st "hReadyV"
blo "158000,3500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReadyV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 2
)
)
)
*68 (CptPort
uid 16893,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16894,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,4625,157000,5375"
)
tg (CPTG
uid 16895,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16896,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,4300,163500,5700"
st "hRespV"
blo "158000,5500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRespV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 4
)
)
)
*69 (CptPort
uid 16897,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16898,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,-1375,173750,-625"
)
tg (CPTG
uid 16899,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16900,0
va (VaSet
font "Verdana,12,0"
)
xt "168500,-1700,172000,-300"
st "hSel"
ju 2
blo "172000,-500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hSel"
t "std_uLogic"
o 8
)
)
)
]
shape (Rectangle
uid 16861,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "157000,-5000,173000,9000"
)
oxt "40000,11000,56000,25000"
ttg (MlTextGroup
uid 16862,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
uid 16863,0
va (VaSet
)
xt "157100,8700,161700,9900"
st "AhbLite"
blo "157100,9700"
tm "BdLibraryNameMgr"
)
*71 (Text
uid 16864,0
va (VaSet
)
xt "157100,9700,167600,10900"
st "ahbMuxConnector"
blo "157100,10700"
tm "CptNameMgr"
)
*72 (Text
uid 16865,0
va (VaSet
)
xt "157100,10700,162000,11900"
st "I_connT"
blo "157100,11700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16866,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16867,0
text (MLText
uid 16868,0
va (VaSet
)
xt "157000,11400,175300,12600"
st "index = gpioIndex    ( positive )  "
)
header ""
)
elements [
(GiElement
name "index"
type "positive"
value "gpioIndex"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*73 (SaComponent
uid 16901,0
optionalChildren [
*74 (CptPort
uid 16910,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16911,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,32625,157000,33375"
)
tg (CPTG
uid 16912,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16913,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,32300,162300,33700"
st "hSelV"
blo "158000,33500"
)
)
thePort (LogicalPort
decl (Decl
n "hSelV"
t "std_ulogic_vector"
b "( 1 TO ahbSlaveNb )"
o 5
)
)
)
*75 (CptPort
uid 16914,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16915,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,34625,157000,35375"
)
tg (CPTG
uid 16916,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16917,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,34300,164200,35700"
st "hRDataV"
blo "158000,35500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRDataV"
t "ahbDataVector"
o 1
)
)
)
*76 (CptPort
uid 16918,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16919,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,36625,173750,37375"
)
tg (CPTG
uid 16920,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16921,0
va (VaSet
font "Verdana,12,0"
)
xt "166500,36300,172000,37700"
st "hReady"
ju 2
blo "172000,37500"
)
)
thePort (LogicalPort
decl (Decl
n "hReady"
t "std_uLogic"
o 7
)
)
)
*77 (CptPort
uid 16922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16923,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,38625,173750,39375"
)
tg (CPTG
uid 16924,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16925,0
va (VaSet
font "Verdana,12,0"
)
xt "167300,38300,172000,39700"
st "hResp"
ju 2
blo "172000,39500"
)
)
thePort (LogicalPort
decl (Decl
n "hResp"
t "std_uLogic"
o 3
)
)
)
*78 (CptPort
uid 16926,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16927,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,34625,173750,35375"
)
tg (CPTG
uid 16928,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16929,0
va (VaSet
font "Verdana,12,0"
)
xt "166600,34300,172000,35700"
st "hRData"
ju 2
blo "172000,35500"
)
)
thePort (LogicalPort
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
)
)
)
*79 (CptPort
uid 16930,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16931,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,36625,157000,37375"
)
tg (CPTG
uid 16932,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16933,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,36300,164300,37700"
st "hReadyV"
blo "158000,37500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReadyV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 2
)
)
)
*80 (CptPort
uid 16934,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16935,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,38625,157000,39375"
)
tg (CPTG
uid 16936,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16937,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,38300,163500,39700"
st "hRespV"
blo "158000,39500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRespV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 4
)
)
)
*81 (CptPort
uid 16938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16939,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,32625,173750,33375"
)
tg (CPTG
uid 16940,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16941,0
va (VaSet
font "Verdana,12,0"
)
xt "168500,32300,172000,33700"
st "hSel"
ju 2
blo "172000,33500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hSel"
t "std_uLogic"
o 8
)
)
)
]
shape (Rectangle
uid 16902,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "157000,29000,173000,43000"
)
oxt "40000,11000,56000,25000"
ttg (MlTextGroup
uid 16903,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*82 (Text
uid 16904,0
va (VaSet
)
xt "157100,42700,161700,43900"
st "AhbLite"
blo "157100,43700"
tm "BdLibraryNameMgr"
)
*83 (Text
uid 16905,0
va (VaSet
)
xt "157100,43700,167600,44900"
st "ahbMuxConnector"
blo "157100,44700"
tm "CptNameMgr"
)
*84 (Text
uid 16906,0
va (VaSet
)
xt "157100,44700,164200,45900"
st "I_connUart"
blo "157100,45700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16907,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16908,0
text (MLText
uid 16909,0
va (VaSet
)
xt "157000,45400,175200,46600"
st "index = uartIndex    ( positive )  "
)
header ""
)
elements [
(GiElement
name "index"
type "positive"
value "uartIndex"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*85 (Net
uid 17490,0
decl (Decl
n "int"
t "std_uLogic"
o 13
suid 87,0
)
declText (MLText
uid 17491,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,91300,16200,92300"
st "SIGNAL int            : std_uLogic"
)
)
*86 (Net
uid 17492,0
decl (Decl
n "upAddress"
t "unsigned"
b "(ahbAddressBitNb-1 DOWNTO 0)"
o 14
suid 88,0
)
declText (MLText
uid 17493,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,92200,30600,93200"
st "SIGNAL upAddress      : unsigned(ahbAddressBitNb-1 DOWNTO 0)"
)
)
*87 (Net
uid 17494,0
decl (Decl
n "upDataOut"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 15
suid 89,0
)
declText (MLText
uid 17495,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,93100,33000,94100"
st "SIGNAL upDataOut      : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*88 (Net
uid 17496,0
decl (Decl
n "upDataIn"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 16
suid 90,0
)
declText (MLText
uid 17497,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,94000,32700,95000"
st "SIGNAL upDataIn       : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*89 (Net
uid 17498,0
decl (Decl
n "upReadStrobe"
t "std_uLogic"
o 17
suid 91,0
)
declText (MLText
uid 17499,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,94900,18200,95900"
st "SIGNAL upReadStrobe   : std_uLogic"
)
)
*90 (Net
uid 17500,0
decl (Decl
n "upWriteStrobe"
t "std_uLogic"
o 18
suid 92,0
)
declText (MLText
uid 17501,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,95800,17900,96800"
st "SIGNAL upWriteStrobe  : std_uLogic"
)
)
*91 (Net
uid 17502,0
decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 DOWNTO 0)"
o 19
suid 93,0
)
declText (MLText
uid 17503,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,96700,30000,97700"
st "SIGNAL hAddr          : unsigned(ahbAddressBitNb-1 DOWNTO 0)"
)
)
*92 (Net
uid 17504,0
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 20
suid 94,0
)
declText (MLText
uid 17505,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,97600,32800,98600"
st "SIGNAL hWData         : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*93 (Net
uid 17506,0
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 21
suid 95,0
)
declText (MLText
uid 17507,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,98500,32600,99500"
st "SIGNAL hRData         : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*94 (Net
uid 17508,0
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 22
suid 96,0
)
declText (MLText
uid 17509,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,99400,32600,100400"
st "SIGNAL hTrans         : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)"
)
)
*95 (Net
uid 17510,0
decl (Decl
n "hSize"
t "std_ulogic_vector"
b "(ahbSizeBitNb-1 DOWNTO 0)"
o 23
suid 97,0
)
declText (MLText
uid 17511,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,100300,31700,101300"
st "SIGNAL hSize          : std_ulogic_vector(ahbSizeBitNb-1 DOWNTO 0)"
)
)
*96 (Net
uid 17512,0
decl (Decl
n "hBurst"
t "std_ulogic_vector"
b "(ahbBurstBitNb-1 DOWNTO 0)"
o 24
suid 98,0
)
declText (MLText
uid 17513,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,101200,32200,102200"
st "SIGNAL hBurst         : std_ulogic_vector(ahbBurstBitNb-1 DOWNTO 0)"
)
)
*97 (Net
uid 17514,0
decl (Decl
n "hProt"
t "std_ulogic_vector"
b "(ahbProtBitNb-1 DOWNTO 0)"
o 25
suid 99,0
)
declText (MLText
uid 17515,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,102100,31700,103100"
st "SIGNAL hProt          : std_ulogic_vector(ahbProtBitNb-1 DOWNTO 0)"
)
)
*98 (Net
uid 17516,0
decl (Decl
n "hWrite"
t "std_uLogic"
o 26
suid 100,0
)
declText (MLText
uid 17517,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,103000,16900,104000"
st "SIGNAL hWrite         : std_uLogic"
)
)
*99 (Net
uid 17518,0
decl (Decl
n "hReady"
t "std_uLogic"
o 27
suid 101,0
)
declText (MLText
uid 17519,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,103900,17400,104900"
st "SIGNAL hReady         : std_uLogic"
)
)
*100 (Net
uid 17520,0
decl (Decl
n "hMastLock"
t "std_uLogic"
o 28
suid 102,0
)
declText (MLText
uid 17521,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,104800,17600,105800"
st "SIGNAL hMastLock      : std_uLogic"
)
)
*101 (Net
uid 17522,0
decl (Decl
n "hResp"
t "std_uLogic"
o 29
suid 103,0
)
declText (MLText
uid 17523,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,105700,17100,106700"
st "SIGNAL hResp          : std_uLogic"
)
)
*102 (Net
uid 17524,0
decl (Decl
n "hClk"
t "std_uLogic"
o 30
suid 104,0
)
declText (MLText
uid 17525,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,106600,16700,107600"
st "SIGNAL hClk           : std_uLogic"
)
)
*103 (Net
uid 17526,0
decl (Decl
n "hReset_n"
t "std_uLogic"
o 31
suid 105,0
)
declText (MLText
uid 17527,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,107500,17500,108500"
st "SIGNAL hReset_n       : std_uLogic"
)
)
*104 (Net
uid 17528,0
decl (Decl
n "hSelV"
t "std_ulogic_vector"
b "(1 TO ahbSlaveNb)"
o 32
suid 106,0
)
declText (MLText
uid 17529,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,108400,27900,109400"
st "SIGNAL hSelV          : std_ulogic_vector(1 TO ahbSlaveNb)"
)
)
*105 (Net
uid 17530,0
decl (Decl
n "hRDataV"
t "ahbDataVector"
o 33
suid 107,0
)
declText (MLText
uid 17531,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,109300,19200,110300"
st "SIGNAL hRDataV        : ahbDataVector"
)
)
*106 (Net
uid 17532,0
decl (Decl
n "hReadyV"
t "std_logic_vector"
b "(1 TO ahbSlaveNb)"
o 34
suid 108,0
)
declText (MLText
uid 17533,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,110200,28200,111200"
st "SIGNAL hReadyV        : std_logic_vector(1 TO ahbSlaveNb)"
)
)
*107 (Net
uid 17534,0
decl (Decl
n "hRespV"
t "std_logic_vector"
b "(1 TO ahbSlaveNb)"
o 35
suid 109,0
)
declText (MLText
uid 17535,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,111100,27900,112100"
st "SIGNAL hRespV         : std_logic_vector(1 TO ahbSlaveNb)"
)
)
*108 (Net
uid 17751,0
decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 126,0
)
declText (MLText
uid 17752,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,56200,13200,57200"
st "clock          : std_ulogic"
)
)
*109 (Net
uid 17753,0
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 127,0
)
declText (MLText
uid 17754,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,55300,13200,56300"
st "reset          : std_ulogic"
)
)
*110 (SaComponent
uid 18307,0
optionalChildren [
*111 (CptPort
uid 18259,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18260,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,24625,189000,25375"
)
tg (CPTG
uid 18261,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18262,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,24300,194500,25700"
st "hAddr"
blo "190000,25500"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 1
suid 2051,0
)
)
)
*112 (CptPort
uid 18263,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18264,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,26625,189000,27375"
)
tg (CPTG
uid 18265,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18266,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,26300,195900,27700"
st "hWData"
blo "190000,27500"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 3
suid 2053,0
)
)
)
*113 (CptPort
uid 18267,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18268,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,34625,189000,35375"
)
tg (CPTG
uid 18269,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18270,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,34300,195400,35700"
st "hRData"
blo "190000,35500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
suid 2054,0
)
)
)
*114 (CptPort
uid 18271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18272,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,30625,189000,31375"
)
tg (CPTG
uid 18273,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18274,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,30300,195000,31700"
st "hWrite"
blo "190000,31500"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_uLogic"
o 4
suid 2055,0
)
)
)
*115 (CptPort
uid 18275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18276,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,28625,189000,29375"
)
tg (CPTG
uid 18277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18278,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,28300,195100,29700"
st "hTrans"
blo "190000,29500"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 2
suid 2059,0
)
)
)
*116 (CptPort
uid 18279,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18280,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,36625,189000,37375"
)
tg (CPTG
uid 18281,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18282,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,36300,195500,37700"
st "hReady"
blo "190000,37500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_uLogic"
o 7
suid 2061,0
)
)
)
*117 (CptPort
uid 18283,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18284,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,38625,189000,39375"
)
tg (CPTG
uid 18285,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18286,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,38300,194700,39700"
st "hResp"
blo "190000,39500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_uLogic"
o 9
suid 2062,0
)
)
)
*118 (CptPort
uid 18287,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18288,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,42625,189000,43375"
)
tg (CPTG
uid 18289,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18290,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,42300,193500,43700"
st "hClk"
blo "190000,43500"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_uLogic"
o 5
suid 2063,0
)
)
)
*119 (CptPort
uid 18291,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18292,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,44625,189000,45375"
)
tg (CPTG
uid 18293,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18294,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,44300,196800,45700"
st "hReset_n"
blo "190000,45500"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_uLogic"
o 8
suid 2064,0
)
)
)
*120 (CptPort
uid 18295,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18296,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,24625,205750,25375"
)
tg (CPTG
uid 18297,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18298,0
va (VaSet
font "Verdana,12,0"
)
xt "200900,24300,204000,25700"
st "TxD"
ju 2
blo "204000,25500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "TxD"
t "std_ulogic"
o 10
suid 2065,0
)
)
)
*121 (CptPort
uid 18299,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18300,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,32625,189000,33375"
)
tg (CPTG
uid 18301,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18302,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,32300,193500,33700"
st "hSel"
blo "190000,33500"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_uLogic"
o 11
suid 2066,0
)
)
)
*122 (CptPort
uid 18303,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18304,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,26625,205750,27375"
)
tg (CPTG
uid 18305,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18306,0
va (VaSet
font "Verdana,12,0"
)
xt "200800,26300,204000,27700"
st "RxD"
ju 2
blo "204000,27500"
)
)
thePort (LogicalPort
decl (Decl
n "RxD"
t "std_ulogic"
o 12
suid 2067,0
)
)
)
]
shape (Rectangle
uid 18308,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "189000,21000,205000,47000"
)
oxt "47000,16000,63000,42000"
ttg (MlTextGroup
uid 18309,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*123 (Text
uid 18310,0
va (VaSet
)
xt "189100,46700,200700,47900"
st "AhbLiteComponents"
blo "189100,47700"
tm "BdLibraryNameMgr"
)
*124 (Text
uid 18311,0
va (VaSet
)
xt "189100,47700,193800,48900"
st "ahbUart"
blo "189100,48700"
tm "CptNameMgr"
)
*125 (Text
uid 18312,0
va (VaSet
)
xt "189100,48700,193900,49900"
st "I_UART"
blo "189100,49700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18313,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18314,0
text (MLText
uid 18315,0
va (VaSet
font "Verdana,8,0"
)
xt "189000,51000,203300,53000"
st "txFifoDepth = 8    ( positive )  
rxFifoDepth = 1    ( positive )  "
)
header ""
)
elements [
(GiElement
name "txFifoDepth"
type "positive"
value "8"
)
(GiElement
name "rxFifoDepth"
type "positive"
value "1"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*126 (PortIoOut
uid 18316,0
shape (CompositeShape
uid 18317,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18318,0
sl 0
ro 270
xt "213500,24625,215000,25375"
)
(Line
uid 18319,0
sl 0
ro 270
xt "213000,25000,213500,25000"
pts [
"213000,25000"
"213500,25000"
]
)
]
)
tg (WTG
uid 18320,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18321,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,24300,219100,25700"
st "TxD"
blo "216000,25500"
tm "WireNameMgr"
)
)
)
*127 (PortIoIn
uid 18340,0
shape (CompositeShape
uid 18341,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18342,0
sl 0
ro 90
xt "213500,26625,215000,27375"
)
(Line
uid 18343,0
sl 0
ro 90
xt "213000,27000,213500,27000"
pts [
"213500,27000"
"213000,27000"
]
)
]
)
tg (WTG
uid 18344,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18345,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,26300,219200,27700"
st "RxD"
blo "216000,27500"
tm "WireNameMgr"
)
)
)
*128 (Net
uid 18346,0
decl (Decl
n "TxD"
t "std_ulogic"
o 1
suid 128,0
)
declText (MLText
uid 18347,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,50800,13400,51800"
st "TxD            : std_ulogic"
)
)
*129 (Net
uid 18348,0
decl (Decl
n "RxD"
t "std_ulogic"
o 2
suid 129,0
)
declText (MLText
uid 18349,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,51700,13500,52700"
st "RxD            : std_ulogic"
)
)
*130 (Net
uid 18350,0
decl (Decl
n "hSelUart"
t "std_uLogic"
o 43
suid 130,0
)
declText (MLText
uid 18351,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,118300,17100,119300"
st "SIGNAL hSelUart       : std_uLogic"
)
)
*131 (Net
uid 18352,0
decl (Decl
n "hRDataUart"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 41
suid 131,0
)
declText (MLText
uid 18353,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,116500,33100,117500"
st "SIGNAL hRDataUart     : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*132 (Net
uid 18354,0
decl (Decl
n "hReadyUart"
t "std_uLogic"
o 47
suid 132,0
)
declText (MLText
uid 18355,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,121900,17900,122900"
st "SIGNAL hReadyUart     : std_uLogic"
)
)
*133 (Net
uid 18356,0
decl (Decl
n "hRespUart"
t "std_uLogic"
o 44
suid 133,0
)
declText (MLText
uid 18357,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,119200,17600,120200"
st "SIGNAL hRespUart      : std_uLogic"
)
)
*134 (SaComponent
uid 18370,0
optionalChildren [
*135 (CptPort
uid 18379,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18380,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,66625,157000,67375"
)
tg (CPTG
uid 18381,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18382,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,66300,162300,67700"
st "hSelV"
blo "158000,67500"
)
)
thePort (LogicalPort
decl (Decl
n "hSelV"
t "std_ulogic_vector"
b "( 1 TO ahbSlaveNb )"
o 5
)
)
)
*136 (CptPort
uid 18383,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18384,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,68625,157000,69375"
)
tg (CPTG
uid 18385,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18386,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,68300,164200,69700"
st "hRDataV"
blo "158000,69500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRDataV"
t "ahbDataVector"
o 1
)
)
)
*137 (CptPort
uid 18387,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18388,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,70625,173750,71375"
)
tg (CPTG
uid 18389,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18390,0
va (VaSet
font "Verdana,12,0"
)
xt "166500,70300,172000,71700"
st "hReady"
ju 2
blo "172000,71500"
)
)
thePort (LogicalPort
decl (Decl
n "hReady"
t "std_uLogic"
o 7
)
)
)
*138 (CptPort
uid 18391,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18392,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,72625,173750,73375"
)
tg (CPTG
uid 18393,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18394,0
va (VaSet
font "Verdana,12,0"
)
xt "167300,72300,172000,73700"
st "hResp"
ju 2
blo "172000,73500"
)
)
thePort (LogicalPort
decl (Decl
n "hResp"
t "std_uLogic"
o 3
)
)
)
*139 (CptPort
uid 18395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18396,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,68625,173750,69375"
)
tg (CPTG
uid 18397,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18398,0
va (VaSet
font "Verdana,12,0"
)
xt "166600,68300,172000,69700"
st "hRData"
ju 2
blo "172000,69500"
)
)
thePort (LogicalPort
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
)
)
)
*140 (CptPort
uid 18399,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18400,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,70625,157000,71375"
)
tg (CPTG
uid 18401,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18402,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,70300,164300,71700"
st "hReadyV"
blo "158000,71500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReadyV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 2
)
)
)
*141 (CptPort
uid 18403,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18404,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,72625,157000,73375"
)
tg (CPTG
uid 18405,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18406,0
va (VaSet
font "Verdana,12,0"
)
xt "158000,72300,163500,73700"
st "hRespV"
blo "158000,73500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRespV"
t "std_logic_vector"
b "(1 to ahbSlaveNb)"
o 4
)
)
)
*142 (CptPort
uid 18407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "173000,66625,173750,67375"
)
tg (CPTG
uid 18409,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18410,0
va (VaSet
font "Verdana,12,0"
)
xt "168500,66300,172000,67700"
st "hSel"
ju 2
blo "172000,67500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hSel"
t "std_uLogic"
o 8
)
)
)
]
shape (Rectangle
uid 18371,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "157000,63000,173000,77000"
)
oxt "40000,11000,56000,25000"
ttg (MlTextGroup
uid 18372,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*143 (Text
uid 18373,0
va (VaSet
)
xt "157100,76700,161700,77900"
st "AhbLite"
blo "157100,77700"
tm "BdLibraryNameMgr"
)
*144 (Text
uid 18374,0
va (VaSet
)
xt "157100,77700,167600,78900"
st "ahbMuxConnector"
blo "157100,78700"
tm "CptNameMgr"
)
*145 (Text
uid 18375,0
va (VaSet
)
xt "157100,78700,164800,79900"
st "I_connBeam"
blo "157100,79700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18376,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18377,0
text (MLText
uid 18378,0
va (VaSet
)
xt "157000,79400,176900,80600"
st "index = beamerIndex    ( positive )  "
)
header ""
)
elements [
(GiElement
name "index"
type "positive"
value "beamerIndex"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*146 (Net
uid 18467,0
decl (Decl
n "hSelBeamer"
t "std_uLogic"
o 42
suid 134,0
)
declText (MLText
uid 18468,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,117400,17900,118400"
st "SIGNAL hSelBeamer     : std_uLogic"
)
)
*147 (Net
uid 18469,0
decl (Decl
n "hRDataBeamer"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 40
suid 135,0
)
declText (MLText
uid 18470,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,115600,33900,116600"
st "SIGNAL hRDataBeamer   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*148 (Net
uid 18471,0
decl (Decl
n "hReadyBeamer"
t "std_uLogic"
o 46
suid 136,0
)
declText (MLText
uid 18472,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,121000,18700,122000"
st "SIGNAL hReadyBeamer   : std_uLogic"
)
)
*149 (Net
uid 18473,0
decl (Decl
n "hRespBeamer"
t "std_uLogic"
o 45
suid 137,0
)
declText (MLText
uid 18474,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,120100,18400,121100"
st "SIGNAL hRespBeamer    : std_uLogic"
)
)
*150 (SaComponent
uid 18666,0
optionalChildren [
*151 (CptPort
uid 18614,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18615,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,-9375,189000,-8625"
)
tg (CPTG
uid 18616,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18617,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,-9700,194500,-8300"
st "hAddr"
blo "190000,-8500"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 1
suid 2051,0
)
)
)
*152 (CptPort
uid 18618,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18619,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,-7375,189000,-6625"
)
tg (CPTG
uid 18620,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18621,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,-7700,195900,-6300"
st "hWData"
blo "190000,-6500"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 3
suid 2053,0
)
)
)
*153 (CptPort
uid 18622,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18623,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,625,189000,1375"
)
tg (CPTG
uid 18624,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18625,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,300,195400,1700"
st "hRData"
blo "190000,1500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 6
suid 2054,0
)
)
)
*154 (CptPort
uid 18626,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18627,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,-3375,189000,-2625"
)
tg (CPTG
uid 18628,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18629,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,-3700,195000,-2300"
st "hWrite"
blo "190000,-2500"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_uLogic"
o 4
suid 2055,0
)
)
)
*155 (CptPort
uid 18630,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18631,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,-5375,189000,-4625"
)
tg (CPTG
uid 18632,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18633,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,-5700,195100,-4300"
st "hTrans"
blo "190000,-4500"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 2
suid 2059,0
)
)
)
*156 (CptPort
uid 18634,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18635,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,2625,189000,3375"
)
tg (CPTG
uid 18636,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18637,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,2300,195500,3700"
st "hReady"
blo "190000,3500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_uLogic"
o 7
suid 2061,0
)
)
)
*157 (CptPort
uid 18638,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18639,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,4625,189000,5375"
)
tg (CPTG
uid 18640,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18641,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,4300,194700,5700"
st "hResp"
blo "190000,5500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_uLogic"
o 9
suid 2062,0
)
)
)
*158 (CptPort
uid 18642,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18643,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,8625,189000,9375"
)
tg (CPTG
uid 18644,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18645,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,8300,193500,9700"
st "hClk"
blo "190000,9500"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_uLogic"
o 5
suid 2063,0
)
)
)
*159 (CptPort
uid 18646,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18647,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,10625,189000,11375"
)
tg (CPTG
uid 18648,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18649,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,10300,196800,11700"
st "hReset_n"
blo "190000,11500"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_uLogic"
o 8
suid 2064,0
)
)
)
*160 (CptPort
uid 18650,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18651,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,-7375,205750,-6625"
)
tg (CPTG
uid 18652,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18653,0
va (VaSet
font "Verdana,12,0"
)
xt "199800,-7700,204000,-6300"
st "ioOut"
ju 2
blo "204000,-6500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 10
suid 2065,0
)
)
)
*161 (CptPort
uid 18654,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18655,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,-1375,189000,-625"
)
tg (CPTG
uid 18656,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18657,0
va (VaSet
font "Verdana,12,0"
)
xt "190000,-1700,193500,-300"
st "hSel"
blo "190000,-500"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_uLogic"
o 11
suid 2066,0
)
)
)
*162 (CptPort
uid 18658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18659,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,-5375,205750,-4625"
)
tg (CPTG
uid 18660,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18661,0
va (VaSet
font "Verdana,12,0"
)
xt "200800,-5700,204000,-4300"
st "ioIn"
ju 2
blo "204000,-4500"
)
)
thePort (LogicalPort
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 12
suid 2067,0
)
)
)
*163 (CptPort
uid 18662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,-9375,205750,-8625"
)
tg (CPTG
uid 18664,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18665,0
va (VaSet
font "Verdana,12,0"
)
xt "200500,-9700,204000,-8300"
st "ioEn"
ju 2
blo "204000,-8500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 13
suid 2068,0
)
)
)
]
shape (Rectangle
uid 18667,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "189000,-13000,205000,13000"
)
oxt "47000,16000,63000,42000"
ttg (MlTextGroup
uid 18668,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*164 (Text
uid 18669,0
va (VaSet
)
xt "189100,12700,200700,13900"
st "AhbLiteComponents"
blo "189100,13700"
tm "BdLibraryNameMgr"
)
*165 (Text
uid 18670,0
va (VaSet
)
xt "189100,13700,193900,14900"
st "ahbGpio"
blo "189100,14700"
tm "CptNameMgr"
)
*166 (Text
uid 18671,0
va (VaSet
)
xt "189100,14700,193800,15900"
st "I_GPIO"
blo "189100,15700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18672,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18673,0
text (MLText
uid 18674,0
va (VaSet
font "Verdana,8,0"
)
xt "189000,17000,201700,18000"
st "ioNb = ioNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*167 (Net
uid 18675,0
decl (Decl
n "hSelGpio"
t "std_uLogic"
o 36
suid 138,0
)
declText (MLText
uid 18676,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,112000,17200,113000"
st "SIGNAL hSelGpio       : std_uLogic"
)
)
*168 (Net
uid 18677,0
decl (Decl
n "hRDataGpio"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 39
suid 139,0
)
declText (MLText
uid 18678,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,114700,33200,115700"
st "SIGNAL hRDataGpio     : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*169 (Net
uid 18679,0
decl (Decl
n "hReadyGpio"
t "std_uLogic"
o 38
suid 140,0
)
declText (MLText
uid 18680,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,113800,18000,114800"
st "SIGNAL hReadyGpio     : std_uLogic"
)
)
*170 (Net
uid 18681,0
decl (Decl
n "hRespGpio"
t "std_uLogic"
o 37
suid 141,0
)
declText (MLText
uid 18682,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,112900,17700,113900"
st "SIGNAL hRespGpio      : std_uLogic"
)
)
*171 (PortIoOut
uid 18683,0
shape (CompositeShape
uid 18684,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18685,0
sl 0
ro 270
xt "213500,-7375,215000,-6625"
)
(Line
uid 18686,0
sl 0
ro 270
xt "213000,-7000,213500,-7000"
pts [
"213000,-7000"
"213500,-7000"
]
)
]
)
tg (WTG
uid 18687,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18688,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,-7700,235600,-6300"
st "ioOut : (ioNb-1 DOWNTO 0)"
blo "216000,-6500"
tm "WireNameMgr"
)
)
)
*172 (PortIoIn
uid 18689,0
shape (CompositeShape
uid 18690,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18691,0
sl 0
ro 90
xt "213500,-5375,215000,-4625"
)
(Line
uid 18692,0
sl 0
ro 90
xt "213000,-5000,213500,-5000"
pts [
"213500,-5000"
"213000,-5000"
]
)
]
)
tg (WTG
uid 18693,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18694,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,-5700,234600,-4300"
st "ioIn : (ioNb-1 DOWNTO 0)"
blo "216000,-4500"
tm "WireNameMgr"
)
)
)
*173 (PortIoOut
uid 18707,0
shape (CompositeShape
uid 18708,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18709,0
sl 0
ro 270
xt "213500,-9375,215000,-8625"
)
(Line
uid 18710,0
sl 0
ro 270
xt "213000,-9000,213500,-9000"
pts [
"213000,-9000"
"213500,-9000"
]
)
]
)
tg (WTG
uid 18711,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18712,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,-9700,234900,-8300"
st "ioEn : (ioNb-1 DOWNTO 0)"
blo "216000,-8500"
tm "WireNameMgr"
)
)
)
*174 (Net
uid 18713,0
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 8
suid 142,0
)
declText (MLText
uid 18714,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,57100,25000,58100"
st "ioEn           : std_ulogic_vector(ioNb-1 DOWNTO 0)"
)
)
*175 (Net
uid 18719,0
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 9
suid 143,0
)
declText (MLText
uid 18720,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,58000,25100,59000"
st "ioOut          : std_ulogic_vector(ioNb-1 DOWNTO 0)"
)
)
*176 (Net
uid 18725,0
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 10
suid 144,0
)
declText (MLText
uid 18726,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,58900,24800,59900"
st "ioIn           : std_ulogic_vector(ioNb-1 DOWNTO 0)"
)
)
*177 (Net
uid 19108,0
decl (Decl
n "intAck"
t "std_ulogic"
o 48
suid 145,0
)
declText (MLText
uid 19109,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,122800,16500,123800"
st "SIGNAL intAck         : std_ulogic"
)
)
*178 (Net
uid 19120,0
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(instructionBitNb-1 DOWNTO 0)"
o 49
suid 151,0
)
declText (MLText
uid 19121,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,123700,32900,124700"
st "SIGNAL instruction    : std_ulogic_vector(instructionBitNb-1 DOWNTO 0)"
)
)
*179 (Net
uid 19122,0
decl (Decl
n "programCounter"
t "unsigned"
b "(programCounterBitNb-1 DOWNTO 0)"
o 50
suid 152,0
)
declText (MLText
uid 19123,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,124600,33600,125600"
st "SIGNAL programCounter : unsigned(programCounterBitNb-1 DOWNTO 0)"
)
)
*180 (Net
uid 19320,0
decl (Decl
n "upEn"
t "std_ulogic"
o 12
suid 160,0
)
declText (MLText
uid 19321,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,90400,16700,91400"
st "SIGNAL upEn           : std_ulogic"
)
)
*181 (HdlText
uid 19389,0
optionalChildren [
*182 (EmbeddedText
uid 19395,0
commentText (CommentText
uid 19396,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 19397,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "12000,-8000,28000,-6000"
)
oxt "0,0,18000,5000"
text (MLText
uid 19398,0
va (VaSet
)
xt "12200,-7800,19800,-6600"
st "
upEn <= '1';

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 19390,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "12000,-9000,28000,-5000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 19391,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*183 (Text
uid 19392,0
va (VaSet
font "Verdana,8,1"
)
xt "11850,-5000,14150,-4000"
st "eb1"
blo "11850,-4200"
tm "HdlTextNameMgr"
)
*184 (Text
uid 19393,0
va (VaSet
font "Verdana,8,1"
)
xt "11850,-4000,13050,-3000"
st "1"
blo "11850,-3200"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 19394,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "12250,-6750,13750,-5250"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*185 (SaComponent
uid 19476,0
optionalChildren [
*186 (CptPort
uid 19428,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19429,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,-5375,44000,-4625"
)
tg (CPTG
uid 19430,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19431,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,-5700,48800,-4300"
st "clock"
blo "45000,-4500"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*187 (CptPort
uid 19432,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19433,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,-3375,44000,-2625"
)
tg (CPTG
uid 19434,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19435,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,-3700,49100,-2300"
st "reset"
blo "45000,-2500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 12,0
)
)
)
*188 (CptPort
uid 19436,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19437,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-7375,60750,-6625"
)
tg (CPTG
uid 19438,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19439,0
va (VaSet
font "Verdana,12,0"
)
xt "50300,-7700,59000,-6300"
st "readStrobe"
ju 2
blo "59000,-6500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "readStrobe"
t "std_uLogic"
o 11
suid 2024,0
)
)
)
*189 (CptPort
uid 19440,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19441,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-5375,60750,-4625"
)
tg (CPTG
uid 19442,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19443,0
va (VaSet
font "Verdana,12,0"
)
xt "50000,-5700,59000,-4300"
st "writeStrobe"
ju 2
blo "59000,-4500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "writeStrobe"
t "std_uLogic"
o 12
suid 2026,0
)
)
)
*190 (CptPort
uid 19444,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19445,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,-7375,44000,-6625"
)
tg (CPTG
uid 19446,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19447,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,-7700,47400,-6300"
st "en"
blo "45000,-6500"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 2027,0
)
)
)
*191 (CptPort
uid 19448,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19449,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,-17375,44000,-16625"
)
tg (CPTG
uid 19450,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19451,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,-17700,49500,-16300"
st "intAck"
blo "45000,-16500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "intAck"
t "std_ulogic"
o 9
suid 2042,0
)
)
)
*192 (CptPort
uid 19452,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19453,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,-19375,44000,-18625"
)
tg (CPTG
uid 19454,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19455,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,-19700,47400,-18300"
st "int"
blo "45000,-18500"
)
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_uLogic"
o 5
suid 2028,0
)
)
)
*193 (CptPort
uid 19456,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19457,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-13375,60750,-12625"
)
tg (CPTG
uid 19458,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19459,0
va (VaSet
font "Verdana,12,0"
)
xt "49400,-13700,59000,-12300"
st "dataAddress"
ju 2
blo "59000,-12500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataAddress"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
suid 2039,0
)
)
)
*194 (CptPort
uid 19460,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19461,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-11375,60750,-10625"
)
tg (CPTG
uid 19462,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19463,0
va (VaSet
font "Verdana,12,0"
)
xt "53000,-11700,59000,-10300"
st "dataOut"
ju 2
blo "59000,-10500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(registerBitNb-1 DOWNTO 0)"
o 8
suid 2040,0
)
)
)
*195 (CptPort
uid 19464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-9375,60750,-8625"
)
tg (CPTG
uid 19466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19467,0
va (VaSet
font "Verdana,12,0"
)
xt "54000,-9700,59000,-8300"
st "dataIn"
ju 2
blo "59000,-8500"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(registerBitNb-1 DOWNTO 0)"
o 2
suid 2050,0
)
)
)
*196 (CptPort
uid 19468,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19469,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-17375,60750,-16625"
)
tg (CPTG
uid 19470,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19471,0
va (VaSet
font "Verdana,12,0"
)
xt "50800,-17700,59000,-16300"
st "instruction"
ju 2
blo "59000,-16500"
)
)
thePort (LogicalPort
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(instructionBitNb-1 DOWNTO 0)"
o 4
suid 2052,0
)
)
)
*197 (CptPort
uid 19472,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19473,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,-19375,60750,-18625"
)
tg (CPTG
uid 19474,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19475,0
va (VaSet
font "Verdana,12,0"
)
xt "49400,-19700,59000,-18300"
st "progCounter"
ju 2
blo "59000,-18500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "progCounter"
t "unsigned"
b "( programCounterBitNb-1 DOWNTO 0 )"
o 10
suid 2053,0
)
)
)
]
shape (Rectangle
uid 19477,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "44000,-23000,60000,-1000"
)
oxt "47000,10000,63000,32000"
ttg (MlTextGroup
uid 19478,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*198 (Text
uid 19479,0
va (VaSet
)
xt "44100,-1300,50100,-100"
st "NanoBlaze"
blo "44100,-300"
tm "BdLibraryNameMgr"
)
*199 (Text
uid 19480,0
va (VaSet
)
xt "44100,-300,53000,900"
st "nanoProcessor"
blo "44100,700"
tm "CptNameMgr"
)
*200 (Text
uid 19481,0
va (VaSet
)
xt "44100,700,47100,1900"
st "I_up"
blo "44100,1700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 19482,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 19483,0
text (MLText
uid 19484,0
va (VaSet
)
xt "44000,1400,80300,9800"
st "addressBitNb           = ahbAddressBitNb           ( positive )  
registerBitNb          = ahbDataBitNb              ( positive )  
registerAddressBitNb   = registerAddressBitNb      ( positive )  
programCounterBitNb    = programCounterBitNb       ( positive )  
stackPointerBitNb      = stackPointerBitNb         ( positive )  
instructionBitNb       = instructionBitNb          ( positive )  
scratchpadAddressBitNb = scratchpadAddressBitNb    ( natural  )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "ahbAddressBitNb"
)
(GiElement
name "registerBitNb"
type "positive"
value "ahbDataBitNb"
)
(GiElement
name "registerAddressBitNb"
type "positive"
value "registerAddressBitNb"
)
(GiElement
name "programCounterBitNb"
type "positive"
value "programCounterBitNb"
)
(GiElement
name "stackPointerBitNb"
type "positive"
value "stackPointerBitNb"
)
(GiElement
name "instructionBitNb"
type "positive"
value "instructionBitNb"
)
(GiElement
name "scratchpadAddressBitNb"
type "natural"
value "scratchpadAddressBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*201 (PortIoOut
uid 19797,0
shape (CompositeShape
uid 19798,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19799,0
sl 0
ro 270
xt "213500,76625,215000,77375"
)
(Line
uid 19800,0
sl 0
ro 270
xt "213000,77000,213500,77000"
pts [
"213000,77000"
"213500,77000"
]
)
]
)
tg (WTG
uid 19801,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19802,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "216000,76500,236900,77900"
st "testOut : (1 TO testOutBitNb)"
blo "216000,77700"
tm "WireNameMgr"
)
)
)
*202 (Net
uid 19811,0
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 11
suid 162,0
)
declText (MLText
uid 19812,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,59800,25000,60800"
st "testOut        : std_ulogic_vector(1 TO testOutBitNb)"
)
)
*203 (SaComponent
uid 20730,0
optionalChildren [
*204 (CptPort
uid 20674,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20675,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,76625,189000,77375"
)
tg (CPTG
uid 20676,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20677,0
va (VaSet
)
xt "190000,76400,193000,77600"
st "hClk"
blo "190000,77400"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_ulogic"
o 13
suid 1,0
)
)
)
*205 (CptPort
uid 20678,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20679,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,58625,189000,59375"
)
tg (CPTG
uid 20680,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20681,0
va (VaSet
)
xt "190000,58400,193700,59600"
st "hAddr"
blo "190000,59400"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 downto 0)"
o 2
suid 2,0
)
)
)
*206 (CptPort
uid 20682,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20683,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,58625,205750,59375"
)
tg (CPTG
uid 20684,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20685,0
va (VaSet
)
xt "201001,58400,204001,59600"
st "outX"
ju 2
blo "204001,59400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 1
suid 3,0
)
)
)
*207 (CptPort
uid 20686,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20687,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,78625,189000,79375"
)
tg (CPTG
uid 20688,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20689,0
va (VaSet
)
xt "190000,78400,195400,79600"
st "hReset_n"
blo "190000,79400"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_ulogic"
o 14
suid 4,0
)
)
)
*208 (CptPort
uid 20690,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20691,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,60625,205750,61375"
)
tg (CPTG
uid 20692,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20693,0
va (VaSet
)
xt "201001,60400,204001,61600"
st "outY"
ju 2
blo "204001,61400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 3
suid 5,0
)
)
)
*209 (CptPort
uid 20694,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20695,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,60625,189000,61375"
)
tg (CPTG
uid 20696,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20697,0
va (VaSet
)
xt "190000,60400,194600,61600"
st "hWData"
blo "190000,61400"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 4
suid 11,0
)
)
)
*210 (CptPort
uid 20698,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20699,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,64625,205750,65375"
)
tg (CPTG
uid 20700,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20701,0
va (VaSet
)
xt "198201,64400,204001,65600"
st "selSinCos"
ju 2
blo "204001,65400"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 5
suid 13,0
)
)
)
*211 (CptPort
uid 20702,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20703,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "205000,76625,205750,77375"
)
tg (CPTG
uid 20704,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20705,0
va (VaSet
)
xt "199400,76400,204000,77600"
st "testOut"
ju 2
blo "204000,77400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 6
suid 2014,0
)
)
)
*212 (CptPort
uid 20706,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20707,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,68625,189000,69375"
)
tg (CPTG
uid 20708,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20709,0
va (VaSet
)
xt "190000,68400,194400,69600"
st "hRData"
blo "190000,69400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 7
suid 2015,0
)
)
)
*213 (CptPort
uid 20710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20711,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,62625,189000,63375"
)
tg (CPTG
uid 20712,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20713,0
va (VaSet
)
xt "190000,62400,194200,63600"
st "hTrans"
blo "190000,63400"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 downto 0)"
o 8
suid 2016,0
)
)
)
*214 (CptPort
uid 20714,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20715,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,64625,189000,65375"
)
tg (CPTG
uid 20716,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20717,0
va (VaSet
)
xt "190000,64400,193900,65600"
st "hWrite"
blo "190000,65400"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_ulogic"
o 9
suid 2017,0
)
)
)
*215 (CptPort
uid 20718,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20719,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,66625,189000,67375"
)
tg (CPTG
uid 20720,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20721,0
va (VaSet
)
xt "190000,66400,192900,67600"
st "hSel"
blo "190000,67400"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_ulogic"
o 10
suid 2018,0
)
)
)
*216 (CptPort
uid 20722,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20723,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,70625,189000,71375"
)
tg (CPTG
uid 20724,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20725,0
va (VaSet
)
xt "190000,70400,194400,71600"
st "hReady"
blo "190000,71400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_ulogic"
o 11
suid 2019,0
)
)
)
*217 (CptPort
uid 20726,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20727,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "188250,72625,189000,73375"
)
tg (CPTG
uid 20728,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20729,0
va (VaSet
)
xt "190000,72400,193800,73600"
st "hResp"
blo "190000,73400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_ulogic"
o 12
suid 2020,0
)
)
)
]
shape (Rectangle
uid 20731,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "189000,55000,205000,81000"
)
oxt "43000,6000,59000,32000"
ttg (MlTextGroup
uid 20732,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*218 (Text
uid 20733,0
va (VaSet
font "Verdana,9,1"
)
xt "189600,80800,198000,82000"
st "SystemOnChip"
blo "189600,81800"
tm "BdLibraryNameMgr"
)
*219 (Text
uid 20734,0
va (VaSet
font "Verdana,9,1"
)
xt "189600,81700,195800,82900"
st "ahbBeamer"
blo "189600,82700"
tm "CptNameMgr"
)
*220 (Text
uid 20735,0
va (VaSet
font "Verdana,9,1"
)
xt "189600,82600,195000,83800"
st "I_beamer"
blo "189600,83600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 20736,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 20737,0
text (MLText
uid 20738,0
va (VaSet
font "Verdana,8,0"
)
xt "189000,84600,214800,86600"
st "patternAddressBitNb = patternAddressBitNb    ( positive )  
testOutBitNb        = testOutBitNb           ( positive )  "
)
header ""
)
elements [
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*221 (SaComponent
uid 20759,0
optionalChildren [
*222 (CptPort
uid 20739,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20740,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,10625,44000,11375"
)
tg (CPTG
uid 20741,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20742,0
va (VaSet
)
xt "45000,10500,49700,11700"
st "address"
blo "45000,11500"
)
)
thePort (LogicalPort
decl (Decl
n "address"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*223 (CptPort
uid 20743,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20744,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,16625,44000,17375"
)
tg (CPTG
uid 20745,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20746,0
va (VaSet
)
xt "45000,16500,48400,17700"
st "clock"
blo "45000,17500"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*224 (CptPort
uid 20747,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20748,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,10625,60750,11375"
)
tg (CPTG
uid 20749,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20750,0
va (VaSet
)
xt "54200,10500,59000,11700"
st "dataOut"
ju 2
blo "59000,11500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "( dataBitNb-1 DOWNTO 0 )"
o 5
suid 3,0
)
)
)
*225 (CptPort
uid 20751,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20752,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,14625,44000,15375"
)
tg (CPTG
uid 20753,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20754,0
va (VaSet
)
xt "45000,14500,46900,15700"
st "en"
blo "45000,15500"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*226 (CptPort
uid 20755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43250,18625,44000,19375"
)
tg (CPTG
uid 20757,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20758,0
va (VaSet
)
xt "45000,18500,48300,19700"
st "reset"
blo "45000,19500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 5,0
)
)
)
]
shape (Rectangle
uid 20760,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "44000,7000,60000,21000"
)
oxt "25000,17000,41000,31000"
ttg (MlTextGroup
uid 20761,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*227 (Text
uid 20762,0
va (VaSet
font "Verdana,8,1"
)
xt "44500,21000,52400,22000"
st "SystemOnChip"
blo "44500,21800"
tm "BdLibraryNameMgr"
)
*228 (Text
uid 20763,0
va (VaSet
font "Verdana,8,1"
)
xt "44500,21900,51600,22900"
st "programRom"
blo "44500,22700"
tm "CptNameMgr"
)
*229 (Text
uid 20764,0
va (VaSet
font "Verdana,8,1"
)
xt "44500,22800,47900,23800"
st "I_rom"
blo "44500,23600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 20765,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 20766,0
text (MLText
uid 20767,0
va (VaSet
font "Verdana,8,0"
)
xt "44000,24200,67500,26200"
st "addressBitNb = programCounterBitNb    ( positive )  
dataBitNb    = instructionBitNb       ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "programCounterBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "instructionBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*230 (Wire
uid 115,0
shape (OrthoPolyLine
uid 116,0
va (VaSet
vasetType 3
)
xt "205750,59000,213000,59000"
pts [
"205750,59000"
"213000,59000"
]
)
start &206
end &12
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 119,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 120,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,57600,213700,59000"
st "outX"
blo "210000,58800"
tm "WireNameMgr"
)
)
on &13
)
*231 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
)
xt "205750,61000,213000,61000"
pts [
"205750,61000"
"213000,61000"
]
)
start &208
end &14
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,59600,213600,61000"
st "outY"
blo "210000,60800"
tm "WireNameMgr"
)
)
on &15
)
*232 (Wire
uid 5086,0
shape (OrthoPolyLine
uid 5087,0
va (VaSet
vasetType 3
)
xt "205750,65000,213000,65000"
pts [
"213000,65000"
"205750,65000"
]
)
start &16
end &210
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5090,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5091,0
va (VaSet
font "Verdana,12,0"
)
xt "208000,63600,214900,65000"
st "selSinCos"
blo "208000,64800"
tm "WireNameMgr"
)
)
on &17
)
*233 (Wire
uid 17076,0
optionalChildren [
*234 (BdJunction
uid 17082,0
ps "OnConnectorStrategy"
shape (Circle
uid 17083,0
va (VaSet
vasetType 1
)
xt "116600,-13399,117400,-12599"
radius 400
)
)
*235 (BdJunction
uid 17084,0
ps "OnConnectorStrategy"
shape (Circle
uid 17085,0
va (VaSet
vasetType 1
)
xt "180600,-9397,181400,-8597"
radius 400
)
)
*236 (BdJunction
uid 17086,0
ps "OnConnectorStrategy"
shape (Circle
uid 17087,0
va (VaSet
vasetType 1
)
xt "180600,24601,181400,25401"
radius 400
)
)
*237 (BdJunction
uid 18513,0
ps "OnConnectorStrategy"
shape (Circle
uid 18514,0
va (VaSet
vasetType 1
)
xt "180600,58600,181400,59400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17077,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-13000,181000,115000"
pts [
"101750,-13000"
"181000,-13000"
"181000,115000"
]
)
start &28
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17080,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17081,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-13000,108250,-11600"
st "hAddr"
blo "103750,-11800"
tm "WireNameMgr"
)
)
on &91
)
*238 (Wire
uid 17092,0
shape (OrthoPolyLine
uid 17093,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "117000,-12996,124250,-1000"
pts [
"117000,-12996"
"117000,-1000"
"124250,-1000"
]
)
start &234
end &56
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17094,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17095,0
va (VaSet
font "Verdana,12,0"
)
xt "118250,-2400,122750,-1000"
st "hAddr"
blo "118250,-1200"
tm "WireNameMgr"
)
)
on &91
)
*239 (Wire
uid 17096,0
shape (OrthoPolyLine
uid 17097,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "181000,-9000,188250,-8997"
pts [
"181000,-8997"
"185000,-8997"
"185000,-9000"
"188250,-9000"
]
)
start &235
end &151
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17098,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17099,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,-10400,186750,-9000"
st "hAddr"
blo "182250,-9200"
tm "WireNameMgr"
)
)
on &91
)
*240 (Wire
uid 17100,0
shape (OrthoPolyLine
uid 17101,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "181000,25000,188250,25001"
pts [
"181000,25001"
"185000,25001"
"185000,25000"
"188250,25000"
]
)
start &236
end &111
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17102,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17103,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,23600,186750,25000"
st "hAddr"
blo "182250,24800"
tm "WireNameMgr"
)
)
on &91
)
*241 (Wire
uid 17104,0
optionalChildren [
*242 (BdJunction
uid 17110,0
ps "OnConnectorStrategy"
shape (Circle
uid 17111,0
va (VaSet
vasetType 1
)
xt "178600,-7399,179400,-6599"
radius 400
)
)
*243 (BdJunction
uid 17112,0
ps "OnConnectorStrategy"
shape (Circle
uid 17113,0
va (VaSet
vasetType 1
)
xt "178600,26600,179400,27400"
radius 400
)
)
*244 (BdJunction
uid 18507,0
ps "OnConnectorStrategy"
shape (Circle
uid 18508,0
va (VaSet
vasetType 1
)
xt "178600,60600,179400,61400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17105,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-11000,179000,115000"
pts [
"101750,-11000"
"179000,-11000"
"179000,115000"
]
)
start &29
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17108,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17109,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-11000,109650,-9600"
st "hWData"
blo "103750,-9800"
tm "WireNameMgr"
)
)
on &92
)
*245 (Wire
uid 17118,0
shape (OrthoPolyLine
uid 17119,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "179000,-7000,188250,-6999"
pts [
"179000,-6999"
"184000,-6999"
"184000,-7000"
"188250,-7000"
]
)
start &242
end &152
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17121,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,-8400,187150,-7000"
st "hWData"
blo "181250,-7200"
tm "WireNameMgr"
)
)
on &92
)
*246 (Wire
uid 17122,0
shape (OrthoPolyLine
uid 17123,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "179000,27000,188250,27000"
pts [
"179000,27000"
"188250,27000"
]
)
start &243
end &112
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17124,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17125,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,25600,187150,27000"
st "hWData"
blo "181250,26800"
tm "WireNameMgr"
)
)
on &92
)
*247 (Wire
uid 17126,0
optionalChildren [
*248 (BdJunction
uid 17132,0
ps "OnConnectorStrategy"
shape (Circle
uid 17133,0
va (VaSet
vasetType 1
)
xt "176600,-5399,177400,-4599"
radius 400
)
)
*249 (BdJunction
uid 17134,0
ps "OnConnectorStrategy"
shape (Circle
uid 17135,0
va (VaSet
vasetType 1
)
xt "176600,28600,177400,29400"
radius 400
)
)
*250 (BdJunction
uid 18501,0
ps "OnConnectorStrategy"
shape (Circle
uid 18502,0
va (VaSet
vasetType 1
)
xt "176600,62600,177400,63400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17127,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-9000,177000,115000"
pts [
"101750,-9000"
"177000,-9000"
"177000,115000"
]
)
start &35
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17130,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17131,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-9000,108850,-7600"
st "hTrans"
blo "103750,-7800"
tm "WireNameMgr"
)
)
on &94
)
*251 (Wire
uid 17140,0
shape (OrthoPolyLine
uid 17141,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177000,-5000,188250,-4999"
pts [
"177000,-4999"
"183000,-4999"
"183000,-5000"
"188250,-5000"
]
)
start &248
end &155
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17142,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17143,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,-6400,187350,-5000"
st "hTrans"
blo "182250,-5200"
tm "WireNameMgr"
)
)
on &94
)
*252 (Wire
uid 17144,0
shape (OrthoPolyLine
uid 17145,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177000,29000,188250,29000"
pts [
"177000,29000"
"188250,29000"
]
)
start &249
end &115
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17146,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17147,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,27600,187350,29000"
st "hTrans"
blo "182250,28800"
tm "WireNameMgr"
)
)
on &94
)
*253 (Wire
uid 17148,0
optionalChildren [
*254 (BdJunction
uid 17154,0
ps "OnConnectorStrategy"
shape (Circle
uid 17155,0
va (VaSet
vasetType 1
)
xt "174600,-3399,175400,-2599"
radius 400
)
)
*255 (BdJunction
uid 17156,0
ps "OnConnectorStrategy"
shape (Circle
uid 17157,0
va (VaSet
vasetType 1
)
xt "174600,30600,175400,31400"
radius 400
)
)
*256 (BdJunction
uid 18495,0
ps "OnConnectorStrategy"
shape (Circle
uid 18496,0
va (VaSet
vasetType 1
)
xt "174600,64600,175400,65400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17149,0
va (VaSet
vasetType 3
)
xt "101750,-7000,175000,115000"
pts [
"101750,-7000"
"175000,-7000"
"175000,115000"
]
)
start &31
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17152,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17153,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-7000,108750,-5600"
st "hWrite"
blo "103750,-5800"
tm "WireNameMgr"
)
)
on &98
)
*257 (Wire
uid 17162,0
shape (OrthoPolyLine
uid 17163,0
va (VaSet
vasetType 3
)
xt "175000,-3000,188250,-2999"
pts [
"175000,-2999"
"182000,-2999"
"182000,-3000"
"188250,-3000"
]
)
start &254
end &154
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17164,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17165,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,-4400,187250,-3000"
st "hWrite"
blo "182250,-3200"
tm "WireNameMgr"
)
)
on &98
)
*258 (Wire
uid 17166,0
shape (OrthoPolyLine
uid 17167,0
va (VaSet
vasetType 3
)
xt "175000,31000,188250,31000"
pts [
"175000,31000"
"188250,31000"
]
)
start &255
end &114
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17168,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17169,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,29600,187250,31000"
st "hWrite"
blo "182250,30800"
tm "WireNameMgr"
)
)
on &98
)
*259 (Wire
uid 17170,0
optionalChildren [
*260 (BdJunction
uid 17174,0
ps "OnConnectorStrategy"
shape (Circle
uid 17175,0
va (VaSet
vasetType 1
)
xt "146600,-1399,147400,-599"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17171,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "141750,-1000,156250,-1000"
pts [
"141750,-1000"
"156250,-1000"
]
)
start &57
end &62
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17172,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17173,0
va (VaSet
font "Verdana,12,0"
)
xt "142000,-2400,146300,-1000"
st "hSelV"
blo "142000,-1200"
tm "WireNameMgr"
)
)
on &104
)
*261 (Wire
uid 17176,0
optionalChildren [
*262 (BdJunction
uid 17180,0
ps "OnConnectorStrategy"
shape (Circle
uid 17181,0
va (VaSet
vasetType 1
)
xt "146600,22600,147400,23400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17177,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "141750,-999,147000,23000"
pts [
"147000,-999"
"147000,23000"
"141750,23000"
]
)
start &260
end &45
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17178,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17179,0
va (VaSet
font "Verdana,12,0"
)
xt "142000,21600,146300,23000"
st "hSelV"
blo "142000,22800"
tm "WireNameMgr"
)
)
on &104
)
*263 (Wire
uid 17182,0
optionalChildren [
*264 (BdJunction
uid 17188,0
ps "OnConnectorStrategy"
shape (Circle
uid 17189,0
va (VaSet
vasetType 1
)
xt "146600,32600,147400,33400"
radius 400
)
)
*265 (BdJunction
uid 18459,0
ps "OnConnectorStrategy"
shape (Circle
uid 18460,0
va (VaSet
vasetType 1
)
xt "146600,66600,147400,67400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17183,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,23000,147000,115000"
pts [
"147000,23000"
"147000,115000"
]
)
start &262
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17186,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17187,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "145600,110000,147000,114300"
st "hSelV"
blo "146800,114300"
tm "WireNameMgr"
)
)
on &104
)
*266 (Wire
uid 17194,0
shape (OrthoPolyLine
uid 17195,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,33000,156250,33000"
pts [
"156250,33000"
"147000,33000"
]
)
start &74
end &264
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17196,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17197,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "151250,31600,155550,33000"
st "hSelV"
blo "151250,32800"
tm "WireNameMgr"
)
)
on &104
)
*267 (Wire
uid 17198,0
optionalChildren [
*268 (BdJunction
uid 17202,0
ps "OnConnectorStrategy"
shape (Circle
uid 17203,0
va (VaSet
vasetType 1
)
xt "148600,26600,149400,27400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17199,0
va (VaSet
vasetType 3
)
xt "141750,1000,156250,27000"
pts [
"141750,27000"
"149000,27000"
"149000,1000"
"156250,1000"
]
)
start &46
end &63
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17200,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17201,0
va (VaSet
font "Verdana,12,0"
)
xt "143750,25600,149950,27000"
st "hRDataV"
blo "143750,26800"
tm "WireNameMgr"
)
)
on &105
)
*269 (Wire
uid 17204,0
optionalChildren [
*270 (BdJunction
uid 17210,0
ps "OnConnectorStrategy"
shape (Circle
uid 17211,0
va (VaSet
vasetType 1
)
xt "148600,34600,149400,35400"
radius 400
)
)
*271 (BdJunction
uid 18461,0
ps "OnConnectorStrategy"
shape (Circle
uid 18462,0
va (VaSet
vasetType 1
)
xt "148600,68600,149400,69400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17205,0
va (VaSet
vasetType 3
)
xt "149000,27000,149000,115000"
pts [
"149000,27000"
"149000,115000"
]
)
start &268
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17208,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17209,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "147600,108000,149000,114200"
st "hRDataV"
blo "148800,114200"
tm "WireNameMgr"
)
)
on &105
)
*272 (Wire
uid 17216,0
shape (OrthoPolyLine
uid 17217,0
va (VaSet
vasetType 3
)
xt "149000,35000,156250,35000"
pts [
"156250,35000"
"149000,35000"
]
)
start &75
end &270
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17218,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17219,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,33600,155450,35000"
st "hRDataV"
blo "149250,34800"
tm "WireNameMgr"
)
)
on &105
)
*273 (Wire
uid 17220,0
optionalChildren [
*274 (BdJunction
uid 17224,0
ps "OnConnectorStrategy"
shape (Circle
uid 17225,0
va (VaSet
vasetType 1
)
xt "150600,28600,151400,29400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17221,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "141750,3000,156250,29000"
pts [
"141750,29000"
"151000,29000"
"151000,3000"
"156250,3000"
]
)
start &50
end &67
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17222,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17223,0
va (VaSet
font "Verdana,12,0"
)
xt "143750,27600,150050,29000"
st "hReadyV"
blo "143750,28800"
tm "WireNameMgr"
)
)
on &106
)
*275 (Wire
uid 17226,0
optionalChildren [
*276 (BdJunction
uid 17232,0
ps "OnConnectorStrategy"
shape (Circle
uid 17233,0
va (VaSet
vasetType 1
)
xt "150600,36600,151400,37400"
radius 400
)
)
*277 (BdJunction
uid 18463,0
ps "OnConnectorStrategy"
shape (Circle
uid 18464,0
va (VaSet
vasetType 1
)
xt "150600,70600,151400,71400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17227,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "151000,29000,151000,115000"
pts [
"151000,29000"
"151000,115000"
]
)
start &274
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17230,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17231,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "149600,108000,151000,114300"
st "hReadyV"
blo "150800,114300"
tm "WireNameMgr"
)
)
on &106
)
*278 (Wire
uid 17238,0
shape (OrthoPolyLine
uid 17239,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "151000,37000,156250,37000"
pts [
"156250,37000"
"151000,37000"
]
)
start &79
end &276
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17240,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17241,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,35600,155550,37000"
st "hReadyV"
blo "149250,36800"
tm "WireNameMgr"
)
)
on &106
)
*279 (Wire
uid 17242,0
optionalChildren [
*280 (BdJunction
uid 17246,0
ps "OnConnectorStrategy"
shape (Circle
uid 17247,0
va (VaSet
vasetType 1
)
xt "152600,30600,153400,31400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17243,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "141750,5000,156250,31000"
pts [
"141750,31000"
"153000,31000"
"153000,5000"
"156250,5000"
]
)
start &51
end &68
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17244,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17245,0
va (VaSet
font "Verdana,12,0"
)
xt "143750,29600,149250,31000"
st "hRespV"
blo "143750,30800"
tm "WireNameMgr"
)
)
on &107
)
*281 (Wire
uid 17248,0
optionalChildren [
*282 (BdJunction
uid 17254,0
ps "OnConnectorStrategy"
shape (Circle
uid 17255,0
va (VaSet
vasetType 1
)
xt "152600,38600,153400,39400"
radius 400
)
)
*283 (BdJunction
uid 18465,0
ps "OnConnectorStrategy"
shape (Circle
uid 18466,0
va (VaSet
vasetType 1
)
xt "152600,72600,153400,73400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17249,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "153000,31000,153000,115000"
pts [
"153000,31000"
"153000,115000"
]
)
start &280
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17253,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "151600,108000,153000,113500"
st "hRespV"
blo "152800,113500"
tm "WireNameMgr"
)
)
on &107
)
*284 (Wire
uid 17260,0
shape (OrthoPolyLine
uid 17261,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "153000,39000,156250,39000"
pts [
"156250,39000"
"153000,39000"
]
)
start &80
end &282
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17262,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17263,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,37600,154750,39000"
st "hRespV"
blo "149250,38800"
tm "WireNameMgr"
)
)
on &107
)
*285 (Wire
uid 17286,0
shape (OrthoPolyLine
uid 17287,0
va (VaSet
vasetType 3
)
xt "36000,-3000,43250,-3000"
pts [
"36000,-3000"
"43250,-3000"
]
)
start &18
end &187
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 17288,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17289,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,-4400,40100,-3000"
st "reset"
blo "36000,-3200"
tm "WireNameMgr"
)
)
on &109
)
*286 (Wire
uid 17290,0
shape (OrthoPolyLine
uid 17291,0
va (VaSet
vasetType 3
)
xt "36000,-5000,43250,-5000"
pts [
"36000,-5000"
"43250,-5000"
]
)
start &19
end &186
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17292,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17293,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,-6400,39800,-5000"
st "clock"
blo "36000,-5200"
tm "WireNameMgr"
)
)
on &108
)
*287 (Wire
uid 17294,0
optionalChildren [
*288 (BdJunction
uid 19318,0
ps "OnConnectorStrategy"
shape (Circle
uid 19319,0
va (VaSet
vasetType 1
)
xt "37600,-7400,38400,-6600"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17295,0
va (VaSet
vasetType 3
)
xt "28000,-7000,43250,-7000"
pts [
"28000,-7000"
"43250,-7000"
]
)
start &181
end &190
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17298,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17299,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,-8400,32000,-7000"
st "upEn"
blo "28000,-7200"
tm "WireNameMgr"
)
)
on &180
)
*289 (Wire
uid 17300,0
shape (OrthoPolyLine
uid 17301,0
va (VaSet
vasetType 3
)
xt "81000,11000,84250,11000"
pts [
"81000,11000"
"84250,11000"
]
)
end &22
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 17304,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17305,0
va (VaSet
font "Verdana,12,0"
)
xt "80000,9600,84100,11000"
st "reset"
blo "80000,10800"
tm "WireNameMgr"
)
)
on &109
)
*290 (Wire
uid 17306,0
shape (OrthoPolyLine
uid 17307,0
va (VaSet
vasetType 3
)
xt "81000,9000,84250,9000"
pts [
"81000,9000"
"84250,9000"
]
)
end &21
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17310,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17311,0
va (VaSet
font "Verdana,12,0"
)
xt "80000,7600,83800,9000"
st "clock"
blo "80000,8800"
tm "WireNameMgr"
)
)
on &108
)
*291 (Wire
uid 17318,0
shape (OrthoPolyLine
uid 17319,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60750,-13000,84250,-13000"
pts [
"60750,-13000"
"84250,-13000"
]
)
start &193
end &25
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17320,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17321,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,-14400,70500,-13000"
st "upAddress"
blo "63000,-13200"
tm "WireNameMgr"
)
)
on &86
)
*292 (Wire
uid 17322,0
shape (OrthoPolyLine
uid 17323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60750,-11000,84250,-11000"
pts [
"60750,-11000"
"84250,-11000"
]
)
start &194
end &26
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17324,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17325,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,-12400,70700,-11000"
st "upDataOut"
blo "63000,-11200"
tm "WireNameMgr"
)
)
on &87
)
*293 (Wire
uid 17326,0
shape (OrthoPolyLine
uid 17327,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60750,-9000,84250,-9000"
pts [
"60750,-9000"
"84250,-9000"
]
)
start &195
end &27
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17328,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17329,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,-10400,69700,-9000"
st "upDataIn"
blo "63000,-9200"
tm "WireNameMgr"
)
)
on &88
)
*294 (Wire
uid 17330,0
shape (OrthoPolyLine
uid 17331,0
va (VaSet
vasetType 3
)
xt "60750,-7000,84250,-7000"
pts [
"60750,-7000"
"84250,-7000"
]
)
start &188
end &23
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17333,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,-8400,73600,-7000"
st "upReadStrobe"
blo "63000,-7200"
tm "WireNameMgr"
)
)
on &89
)
*295 (Wire
uid 17334,0
shape (OrthoPolyLine
uid 17335,0
va (VaSet
vasetType 3
)
xt "60750,-5000,84250,-5000"
pts [
"60750,-5000"
"84250,-5000"
]
)
start &189
end &24
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17337,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,-6400,73800,-5000"
st "upWriteStrobe"
blo "63000,-5200"
tm "WireNameMgr"
)
)
on &90
)
*296 (Wire
uid 17338,0
shape (OrthoPolyLine
uid 17339,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,3000,124250,27000"
pts [
"101750,3000"
"115000,3000"
"115000,27000"
"124250,27000"
]
)
start &30
end &49
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17340,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17341,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,1600,109150,3000"
st "hRData"
blo "103750,2800"
tm "WireNameMgr"
)
)
on &93
)
*297 (Wire
uid 17342,0
shape (OrthoPolyLine
uid 17343,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-5000,113000,-5000"
pts [
"101750,-5000"
"113000,-5000"
]
)
start &32
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17347,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-6400,107950,-5000"
st "hSize"
blo "103750,-5200"
tm "WireNameMgr"
)
)
on &95
)
*298 (Wire
uid 17348,0
shape (OrthoPolyLine
uid 17349,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-3000,113000,-3000"
pts [
"101750,-3000"
"113000,-3000"
]
)
start &33
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17352,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17353,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-4400,108650,-3000"
st "hBurst"
blo "103750,-3200"
tm "WireNameMgr"
)
)
on &96
)
*299 (Wire
uid 17354,0
shape (OrthoPolyLine
uid 17355,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "101750,-1000,113000,-1000"
pts [
"101750,-1000"
"113000,-1000"
]
)
start &34
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17358,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17359,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-2400,107950,-1000"
st "hProt"
blo "103750,-1200"
tm "WireNameMgr"
)
)
on &97
)
*300 (Wire
uid 17360,0
shape (OrthoPolyLine
uid 17361,0
va (VaSet
vasetType 3
)
xt "101750,5000,124250,29000"
pts [
"101750,5000"
"113000,5000"
"113000,29000"
"124250,29000"
]
)
start &37
end &47
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17363,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,3600,109250,5000"
st "hReady"
blo "103750,4800"
tm "WireNameMgr"
)
)
on &99
)
*301 (Wire
uid 17364,0
shape (OrthoPolyLine
uid 17365,0
va (VaSet
vasetType 3
)
xt "101750,1000,113000,1000"
pts [
"101750,1000"
"113000,1000"
]
)
start &36
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17368,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17369,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,-400,111150,1000"
st "hMastLock"
blo "103750,800"
tm "WireNameMgr"
)
)
on &100
)
*302 (Wire
uid 17370,0
shape (OrthoPolyLine
uid 17371,0
va (VaSet
vasetType 3
)
xt "101750,7000,124250,31000"
pts [
"101750,7000"
"111000,7000"
"111000,31000"
"124250,31000"
]
)
start &38
end &48
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17373,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,5600,108450,7000"
st "hResp"
blo "103750,6800"
tm "WireNameMgr"
)
)
on &101
)
*303 (Wire
uid 17374,0
shape (OrthoPolyLine
uid 17375,0
va (VaSet
vasetType 3
)
xt "101750,9000,109000,9000"
pts [
"101750,9000"
"109000,9000"
]
)
start &39
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17378,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17379,0
va (VaSet
font "Verdana,12,0"
)
xt "104000,7600,107500,9000"
st "hClk"
blo "104000,8800"
tm "WireNameMgr"
)
)
on &102
)
*304 (Wire
uid 17380,0
shape (OrthoPolyLine
uid 17381,0
va (VaSet
vasetType 3
)
xt "101750,11000,109000,11000"
pts [
"101750,11000"
"109000,11000"
]
)
start &40
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17384,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17385,0
va (VaSet
font "Verdana,12,0"
)
xt "103750,9600,110550,11000"
st "hReset_n"
blo "103750,10800"
tm "WireNameMgr"
)
)
on &103
)
*305 (Wire
uid 17386,0
shape (OrthoPolyLine
uid 17387,0
va (VaSet
vasetType 3
)
xt "185000,9000,188250,9000"
pts [
"188250,9000"
"185000,9000"
]
)
start &158
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17390,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17391,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,7600,186500,9000"
st "hClk"
blo "183000,8800"
tm "WireNameMgr"
)
)
on &102
)
*306 (Wire
uid 17392,0
shape (OrthoPolyLine
uid 17393,0
va (VaSet
vasetType 3
)
xt "185000,11000,188250,11000"
pts [
"188250,11000"
"185000,11000"
]
)
start &159
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17396,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17397,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,9600,189800,11000"
st "hReset_n"
blo "183000,10800"
tm "WireNameMgr"
)
)
on &103
)
*307 (Wire
uid 17398,0
shape (OrthoPolyLine
uid 17399,0
va (VaSet
vasetType 3
)
xt "173750,-1000,188250,-1000"
pts [
"173750,-1000"
"188250,-1000"
]
)
start &69
end &161
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17400,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17401,0
va (VaSet
font "Verdana,12,0"
)
xt "182000,-2400,188300,-1000"
st "hSelGpio"
blo "182000,-1200"
tm "WireNameMgr"
)
)
on &167
)
*308 (Wire
uid 17402,0
shape (OrthoPolyLine
uid 17403,0
va (VaSet
vasetType 3
)
xt "173750,5000,188250,5000"
pts [
"188250,5000"
"173750,5000"
]
)
start &157
end &65
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17404,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17405,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,3600,188750,5000"
st "hRespGpio"
blo "181250,4800"
tm "WireNameMgr"
)
)
on &170
)
*309 (Wire
uid 17406,0
shape (OrthoPolyLine
uid 17407,0
va (VaSet
vasetType 3
)
xt "173750,3000,188250,3000"
pts [
"188250,3000"
"173750,3000"
]
)
start &156
end &64
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17408,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17409,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,1600,190350,3000"
st "hReadyGpio"
blo "181250,2800"
tm "WireNameMgr"
)
)
on &169
)
*310 (Wire
uid 17410,0
shape (OrthoPolyLine
uid 17411,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "173750,1000,188250,1000"
pts [
"188250,1000"
"173750,1000"
]
)
start &153
end &66
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17413,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,-400,190250,1000"
st "hRDataGpio"
blo "181250,800"
tm "WireNameMgr"
)
)
on &168
)
*311 (Wire
uid 17456,0
shape (OrthoPolyLine
uid 17457,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "173750,35000,188250,35000"
pts [
"188250,35000"
"173750,35000"
]
)
start &113
end &78
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 17458,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17459,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,33600,190150,35000"
st "hRDataUart"
blo "181250,34800"
tm "WireNameMgr"
)
)
on &131
)
*312 (Wire
uid 17460,0
shape (OrthoPolyLine
uid 17461,0
va (VaSet
vasetType 3
)
xt "173750,33000,188250,33000"
pts [
"173750,33000"
"188250,33000"
]
)
start &81
end &121
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17462,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17463,0
va (VaSet
font "Verdana,12,0"
)
xt "182000,31600,188200,33000"
st "hSelUart"
blo "182000,32800"
tm "WireNameMgr"
)
)
on &130
)
*313 (Wire
uid 17464,0
shape (OrthoPolyLine
uid 17465,0
va (VaSet
vasetType 3
)
xt "173750,39000,188250,39000"
pts [
"188250,39000"
"173750,39000"
]
)
start &117
end &77
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17466,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17467,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,37600,188650,39000"
st "hRespUart"
blo "181250,38800"
tm "WireNameMgr"
)
)
on &133
)
*314 (Wire
uid 17468,0
shape (OrthoPolyLine
uid 17469,0
va (VaSet
vasetType 3
)
xt "173750,37000,188250,37000"
pts [
"188250,37000"
"173750,37000"
]
)
start &116
end &76
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 17470,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17471,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,35600,190250,37000"
st "hReadyUart"
blo "181250,36800"
tm "WireNameMgr"
)
)
on &132
)
*315 (Wire
uid 17472,0
shape (OrthoPolyLine
uid 17473,0
va (VaSet
vasetType 3
)
xt "185000,45000,188250,45000"
pts [
"188250,45000"
"185000,45000"
]
)
start &119
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17477,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,43600,189800,45000"
st "hReset_n"
blo "183000,44800"
tm "WireNameMgr"
)
)
on &103
)
*316 (Wire
uid 17478,0
shape (OrthoPolyLine
uid 17479,0
va (VaSet
vasetType 3
)
xt "185000,43000,188250,43000"
pts [
"188250,43000"
"185000,43000"
]
)
start &118
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 17482,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17483,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,41600,186500,43000"
st "hClk"
blo "183000,42800"
tm "WireNameMgr"
)
)
on &102
)
*317 (Wire
uid 18322,0
shape (OrthoPolyLine
uid 18323,0
va (VaSet
vasetType 3
)
xt "205750,25000,213000,25000"
pts [
"205750,25000"
"213000,25000"
]
)
start &120
end &126
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18327,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,23600,213100,25000"
st "TxD"
blo "210000,24800"
tm "WireNameMgr"
)
)
on &128
)
*318 (Wire
uid 18334,0
shape (OrthoPolyLine
uid 18335,0
va (VaSet
vasetType 3
)
xt "205750,27000,213000,27000"
pts [
"205750,27000"
"213000,27000"
]
)
start &122
end &127
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18339,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,25600,213200,27000"
st "RxD"
blo "210000,26800"
tm "WireNameMgr"
)
)
on &129
)
*319 (Wire
uid 18411,0
shape (OrthoPolyLine
uid 18412,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,67000,156250,67000"
pts [
"156250,67000"
"147000,67000"
]
)
start &135
end &265
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18415,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18416,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "151250,65600,155550,67000"
st "hSelV"
blo "151250,66800"
tm "WireNameMgr"
)
)
on &104
)
*320 (Wire
uid 18417,0
shape (OrthoPolyLine
uid 18418,0
va (VaSet
vasetType 3
)
xt "149000,69000,156250,69000"
pts [
"156250,69000"
"149000,69000"
]
)
start &136
end &271
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18421,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18422,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,67600,155450,69000"
st "hRDataV"
blo "149250,68800"
tm "WireNameMgr"
)
)
on &105
)
*321 (Wire
uid 18423,0
shape (OrthoPolyLine
uid 18424,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "151000,71000,156250,71000"
pts [
"156250,71000"
"151000,71000"
]
)
start &140
end &277
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18427,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18428,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,69600,155550,71000"
st "hReadyV"
blo "149250,70800"
tm "WireNameMgr"
)
)
on &106
)
*322 (Wire
uid 18429,0
shape (OrthoPolyLine
uid 18430,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "153000,73000,156250,73000"
pts [
"156250,73000"
"153000,73000"
]
)
start &141
end &283
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18433,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18434,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "149250,71600,154750,73000"
st "hRespV"
blo "149250,72800"
tm "WireNameMgr"
)
)
on &107
)
*323 (Wire
uid 18435,0
shape (OrthoPolyLine
uid 18436,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "173750,69000,188250,69000"
pts [
"188250,69000"
"173750,69000"
]
)
start &212
end &139
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 18439,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18440,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,67600,192250,69000"
st "hRDataBeamer"
blo "181250,68800"
tm "WireNameMgr"
)
)
on &147
)
*324 (Wire
uid 18441,0
shape (OrthoPolyLine
uid 18442,0
va (VaSet
vasetType 3
)
xt "173750,67000,188250,67000"
pts [
"173750,67000"
"188250,67000"
]
)
start &142
end &215
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 18445,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18446,0
va (VaSet
font "Verdana,12,0"
)
xt "182000,65600,191100,67000"
st "hSelBeamer"
blo "182000,66800"
tm "WireNameMgr"
)
)
on &146
)
*325 (Wire
uid 18447,0
shape (OrthoPolyLine
uid 18448,0
va (VaSet
vasetType 3
)
xt "173750,73000,188250,73000"
pts [
"188250,73000"
"173750,73000"
]
)
start &217
end &138
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 18451,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18452,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,71600,191550,73000"
st "hRespBeamer"
blo "181250,72800"
tm "WireNameMgr"
)
)
on &149
)
*326 (Wire
uid 18453,0
shape (OrthoPolyLine
uid 18454,0
va (VaSet
vasetType 3
)
xt "173750,71000,188250,71000"
pts [
"188250,71000"
"173750,71000"
]
)
start &216
end &137
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 18457,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18458,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,69600,192350,71000"
st "hReadyBeamer"
blo "181250,70800"
tm "WireNameMgr"
)
)
on &148
)
*327 (Wire
uid 18475,0
shape (OrthoPolyLine
uid 18476,0
va (VaSet
vasetType 3
)
xt "185000,79000,188250,79000"
pts [
"188250,79000"
"185000,79000"
]
)
start &207
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 18481,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18482,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,77600,189800,79000"
st "hReset_n"
blo "183000,78800"
tm "WireNameMgr"
)
)
on &103
)
*328 (Wire
uid 18483,0
shape (OrthoPolyLine
uid 18484,0
va (VaSet
vasetType 3
)
xt "185000,77000,188250,77000"
pts [
"188250,77000"
"185000,77000"
]
)
start &204
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 18489,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18490,0
va (VaSet
font "Verdana,12,0"
)
xt "183000,75600,186500,77000"
st "hClk"
blo "183000,76800"
tm "WireNameMgr"
)
)
on &102
)
*329 (Wire
uid 18491,0
shape (OrthoPolyLine
uid 18492,0
va (VaSet
vasetType 3
)
xt "175000,65000,188250,65000"
pts [
"175000,65000"
"188250,65000"
]
)
start &256
end &214
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18493,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18494,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,63600,187250,65000"
st "hWrite"
blo "182250,64800"
tm "WireNameMgr"
)
)
on &98
)
*330 (Wire
uid 18497,0
shape (OrthoPolyLine
uid 18498,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177000,63000,188250,63000"
pts [
"177000,63000"
"188250,63000"
]
)
start &250
end &213
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18499,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18500,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,61600,187350,63000"
st "hTrans"
blo "182250,62800"
tm "WireNameMgr"
)
)
on &94
)
*331 (Wire
uid 18503,0
shape (OrthoPolyLine
uid 18504,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "179000,61000,188250,61000"
pts [
"179000,61000"
"188250,61000"
]
)
start &244
end &209
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18505,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18506,0
va (VaSet
font "Verdana,12,0"
)
xt "181250,59600,187150,61000"
st "hWData"
blo "181250,60800"
tm "WireNameMgr"
)
)
on &92
)
*332 (Wire
uid 18509,0
shape (OrthoPolyLine
uid 18510,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "181000,59000,188250,59000"
pts [
"181000,59000"
"188250,59000"
]
)
start &237
end &205
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18512,0
va (VaSet
font "Verdana,12,0"
)
xt "182250,57600,186750,59000"
st "hAddr"
blo "182250,58800"
tm "WireNameMgr"
)
)
on &91
)
*333 (Wire
uid 18715,0
shape (OrthoPolyLine
uid 18716,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "205750,-9000,213000,-9000"
pts [
"213000,-9000"
"205750,-9000"
]
)
start &173
end &163
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 18717,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18718,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,-10400,213500,-9000"
st "ioEn"
blo "210000,-9200"
tm "WireNameMgr"
)
)
on &174
)
*334 (Wire
uid 18721,0
shape (OrthoPolyLine
uid 18722,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "205750,-7000,213000,-7000"
pts [
"213000,-7000"
"205750,-7000"
]
)
start &171
end &160
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 18723,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18724,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,-8400,214200,-7000"
st "ioOut"
blo "210000,-7200"
tm "WireNameMgr"
)
)
on &175
)
*335 (Wire
uid 18727,0
shape (OrthoPolyLine
uid 18728,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "205750,-5000,213000,-5000"
pts [
"213000,-5000"
"205750,-5000"
]
)
start &172
end &162
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 18729,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18730,0
va (VaSet
font "Verdana,12,0"
)
xt "210000,-6400,213200,-5000"
st "ioIn"
blo "210000,-5200"
tm "WireNameMgr"
)
)
on &176
)
*336 (Wire
uid 19070,0
shape (OrthoPolyLine
uid 19071,0
va (VaSet
vasetType 3
)
xt "36000,-17000,43250,-17000"
pts [
"43250,-17000"
"36000,-17000"
]
)
start &191
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19075,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,-18400,40500,-17000"
st "intAck"
blo "36000,-17200"
tm "WireNameMgr"
)
)
on &177
)
*337 (Wire
uid 19076,0
shape (OrthoPolyLine
uid 19077,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60750,-17000,69000,11000"
pts [
"60750,-17000"
"69000,-17000"
"69000,11000"
"60750,11000"
]
)
start &196
end &224
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 19078,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19079,0
va (VaSet
font "Verdana,12,0"
)
xt "62750,-18400,70950,-17000"
st "instruction"
blo "62750,-17200"
tm "WireNameMgr"
)
)
on &178
)
*338 (Wire
uid 19080,0
shape (OrthoPolyLine
uid 19081,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40000,-19000,65000,11000"
pts [
"60750,-19000"
"65000,-19000"
"65000,3000"
"40000,3000"
"40000,11000"
"43250,11000"
]
)
start &197
end &222
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 19082,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19083,0
va (VaSet
font "Verdana,12,0"
)
xt "62000,-20400,74000,-19000"
st "programCounter"
blo "62000,-19200"
tm "WireNameMgr"
)
)
on &179
)
*339 (Wire
uid 19084,0
shape (OrthoPolyLine
uid 19085,0
va (VaSet
vasetType 3
)
xt "36000,-19000,43250,-19000"
pts [
"36000,-19000"
"43250,-19000"
]
)
end &192
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19088,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19089,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,-20400,38400,-19000"
st "int"
blo "36000,-19200"
tm "WireNameMgr"
)
)
on &85
)
*340 (Wire
uid 19298,0
shape (OrthoPolyLine
uid 19299,0
va (VaSet
vasetType 3
)
xt "40000,19000,43250,19000"
pts [
"40000,19000"
"43250,19000"
]
)
end &226
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19304,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19305,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,17600,43100,19000"
st "reset"
blo "39000,18800"
tm "WireNameMgr"
)
)
on &109
)
*341 (Wire
uid 19306,0
shape (OrthoPolyLine
uid 19307,0
va (VaSet
vasetType 3
)
xt "40000,17000,43250,17000"
pts [
"40000,17000"
"43250,17000"
]
)
end &223
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19312,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19313,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,15600,42800,17000"
st "clock"
blo "39000,16800"
tm "WireNameMgr"
)
)
on &108
)
*342 (Wire
uid 19314,0
shape (OrthoPolyLine
uid 19315,0
va (VaSet
vasetType 3
)
xt "38000,-6997,43250,15000"
pts [
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start &288
end &225
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19316,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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xt "40250,13600,44250,15000"
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blo "40250,14800"
tm "WireNameMgr"
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on &180
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uid 19803,0
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va (VaSet
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xt "205750,77000,213000,77000"
pts [
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start &211
end &201
sat 32
eat 32
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stc 0
st 0
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uid 19807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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st "testOut"
blo "208000,76800"
tm "WireNameMgr"
)
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on &202
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bg "65535,65535,65535"
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isActive 1
xSpacing 1000
xySpacing 1000
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yShown 1
color "26368,26368,26368"
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "0,-24200"
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va (VaSet
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LIBRARY AhbLite;
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tm "PackageList"
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stg "VerticalLayoutStrategy"
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va (VaSet
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va (VaSet
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uid 48,0
va (VaSet
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st "`resetall
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uid 49,0
va (VaSet
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uid 52,0
va (VaSet
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useAdjustTo 0
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va (VaSet
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st "
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tm "CommentText"
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visibleWidth 14600
)
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shape (ZoomableIcon
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lineColor "0,0,32768"
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xt "450,2150,1450,3150"
st "
Text
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tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
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va (VaSet
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lineColor "32768,0,0"
lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
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xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
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xt "0,0,8000,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*355 (Text
va (VaSet
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xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*356 (Text
va (VaSet
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xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
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)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
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xt "1700,13200,1700,13200"
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header ""
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elements [
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defaultMWComponent (MWC
shape (Rectangle
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "1000,5300"
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*359 (Text
va (VaSet
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xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
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header ""
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elements [
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pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
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tm "BdLibraryNameMgr"
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xt "1250,4500,6750,5500"
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blo "1250,5300"
tm "CptNameMgr"
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va (VaSet
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tm "InstanceNameMgr"
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matrix (Matrix
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xt "-5750,1500,-5750,1500"
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header ""
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elements [
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ttg (MlTextGroup
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va (VaSet
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*365 (Text
va (VaSet
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tm "InstanceNameMgr"
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va (VaSet
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st "I0"
blo "450,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
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xt "-6550,1500,-6550,1500"
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header ""
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elements [
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entityPath ""
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defaultHdlText (HdlText
shape (Rectangle
va (VaSet
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xt "0,0,8000,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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tm "HdlTextNameMgr"
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va (VaSet
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xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
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)
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commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "0,0,18000,5000"
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text (MLText
va (VaSet
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xt "200,200,3200,1400"
st "
Text
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tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
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xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
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xt "-300,-500,300,500"
st "G"
blo "-300,300"
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ps "OnConnectorStrategy"
shape (Line2D
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va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
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)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
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xt "-400,-400,400,400"
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)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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ro 270
xt "-2000,-375,-500,375"
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ro 270
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tg (WTG
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stg "STSignalDisplayStrategy"
f (Text
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xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
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)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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)
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)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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font "Verdana,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
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]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
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]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*372 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Verdana,8,1"
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*374 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,49000,7000,50000"
st "Declarations"
blo "0,49800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,49900,3400,50900"
st "Ports:"
blo "0,50700"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,60700,4800,61700"
st "Pre User:"
blo "0,61500"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,61600,29500,92600"
st "constant programCounterBitNb: positive := 10;
constant instructionBitNb: positive := 26;
constant stackPointerBitNb: positive := 4;
constant registerAddressBitNb: positive := 4;
constant scratchpadAddressBitNb: natural := 0;

constant signalBitNb: positive := 16;
constant updatePeriodBitNb : positive := 16;

constant gpioIndex: positive := 1;
constant uartIndex: positive := gpioIndex+1;
constant beamerIndex: positive := uartIndex+1;

constant ahbMemoryLocation : ahbMemoryLocationVector := (
  gpioIndex => (
    baseAddress => 16#0000#,
    addressMask => 16#10000# - 16#0002#
  ),
  uartIndex => (
    baseAddress => 16#0010#,
    addressMask => 16#10000# - 16#0004#
  ),
  beamerIndex => (
    baseAddress => 16#0020#,
    addressMask => 16#10000# - 16#0004#
  ),
  others => (
    baseAddress => 16#FFFF#,
    addressMask => 16#0000#
  )
);"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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)
xt "0,89500,9000,90500"
st "Diagram Signals:"
blo "0,90300"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,49000,6000,50000"
st "Post User:"
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