480 lines
20 KiB
VHDL
480 lines
20 KiB
VHDL
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE test OF ahbBeamer_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal reset_int: std_uLogic;
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-- test information
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signal testSeparator : string(1 to 80) := (others => '-');
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signal errorTopSeparator : string(1 to 80) := (others => '#');
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signal bottomSeparator : string(1 to 80) := (others => '.');
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signal indentation : string(1 to 2) := (others => ' ');
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signal noteInformation : string(1 to 9) := (others => ' ');
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signal errorInformation : string(1 to 10) := (others => ' ');
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signal failureInformation : string(1 to 12) := (others => ' ');
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signal testInformation : string(1 to 50) := (others => ' ');
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-- register definition
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constant controlRegisterAddress: natural := 0;
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constant controlRun: natural := 2#001#;
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constant controlUpdatePattern: natural := 2#010#;
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constant controlInterpolateLinear: natural := 2#100#;
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constant speedRegisterAddress: natural := 1;
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constant xFifoRegisterAddress: natural := 2;
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constant yFifoRegisterAddress: natural := 3;
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signal updatePeriod: natural := 1;
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signal patternLength: natural := 32;
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-- AMBA bus access
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constant registerWriteDelay: time := 4*clockPeriod;
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signal registerAddress: natural;
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signal registerDataOut, registerDataIn: integer;
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signal registerWrite: std_uLogic;
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signal registerRead: std_uLogic;
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-- UART access
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constant baudPeriodNb: positive := 4;
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signal uartData: integer;
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signal uartSend: std_uLogic;
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-- functions
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function clearBits (word, bits : natural) return natural is
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variable andMask: unsigned(hRData'range);
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begin
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andMask := not(to_unsigned(bits, hRData'length));
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return to_integer(to_unsigned(word, hRData'length) and andMask);
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end clearBits;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset_int <= '1', '0' after 2*clockPeriod;
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hReset_n <= not(reset_int);
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reset <= reset_int;
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clock_int <= not clock_int after clockPeriod/2;
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hClk <= transport clock_int after clockPeriod*9.0/10.0;
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clock <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- test sequence
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testSequence: process
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begin
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selSinCos <= '0';
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registerAddress <= 0;
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registerDataOut <= 0;
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registerWrite <= '0';
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registerRead <= '0';
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uartSend <= '0';
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wait for 100 ns;
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print(cr & cr & cr & cr);
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----------------------------------------------------------------------------
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-- test control register
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wait for 1 us - now;
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testInformation <= pad("Testing control register", testInformation'length);
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wait for 0 ns;
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print(testSeparator & cr & testInformation);
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-- set control register bits
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerDataOut <= controlRun + controlUpdatePattern + controlInterpolateLinear;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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-- readback control register
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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wait for 3*clockPeriod;
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assert(registerDataIn = controlRun + controlUpdatePattern + controlInterpolateLinear)
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report "Control register write / readback error"
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severity error;
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wait for registerWriteDelay;
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-- stop running and pattern update
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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wait for 3*clockPeriod;
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registerDataOut <= clearBits(registerDataIn, controlRun + controlUpdatePattern);
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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----------------------------------------------------------------------------
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-- test speed register
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wait for 2 us - now;
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testInformation <= pad("Testing speed register", testInformation'length);
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wait for 0 ns;
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print(testSeparator & cr & testInformation);
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-- set speed count value
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wait until rising_edge(clock_int);
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registerAddress <= speedRegisterAddress;
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registerDataOut <= updatePeriod;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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-- readback speed count
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wait until rising_edge(clock_int);
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registerAddress <= speedRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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wait for 3*clockPeriod;
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assert(registerDataIn = updatePeriod)
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report "Speed register write / readback error"
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severity error;
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wait for registerWriteDelay;
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----------------------------------------------------------------------------
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-- write sinewave data points to RAM
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wait for 3 us - now;
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testInformation <= pad("Writing sinewaves to RAM", testInformation'length);
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wait for 0 ns;
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print(testSeparator & cr & testInformation);
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-- start pattern update
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerDataOut <= controlUpdatePattern;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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-- write X FIFO values
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wait until rising_edge(clock_int);
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registerAddress <= xFifoRegisterAddress;
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registerDataOut <= 16#0000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7FFF#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#0000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7FFF#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 10*registerWriteDelay;
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-- write Y FIFO values
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wait until rising_edge(clock_int);
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registerAddress <= yFifoRegisterAddress;
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registerDataOut <= 16#7FFF#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#0000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7FFF#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= -16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#0000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#18F9#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#30FB#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#471C#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#5A82#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#6A6D#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7641#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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registerDataOut <= 16#7D89#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 10*registerWriteDelay;
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-- end pattern update
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerDataOut <= 0;
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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----------------------------------------------------------------------------
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-- playing waveforms
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wait for 7 us - now;
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testInformation <= pad("Playing waveforms", testInformation'length);
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wait for 0 ns;
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print(testSeparator & cr & testInformation);
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-- start run
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wait until rising_edge(clock_int);
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registerAddress <= controlRegisterAddress;
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registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb);
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registerWrite <= '1', '0' after clockPeriod;
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wait for registerWriteDelay;
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-- run for some time
|
||
|
|
wait for 250 us - now;
|
||
|
|
-- stop run
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= controlRegisterAddress;
|
||
|
|
registerDataOut <= 0;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
-- play data points to RAM for overflow
|
||
|
|
wait for 300 us - now;
|
||
|
|
testInformation <= pad(
|
||
|
|
"Writing waveform to RAM for overflow", testInformation'length
|
||
|
|
);
|
||
|
|
wait for 0 ns;
|
||
|
|
print(testSeparator & cr & testInformation);
|
||
|
|
-- start pattern update
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= controlRegisterAddress;
|
||
|
|
registerDataOut <= controlUpdatePattern;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
-- write X FIFO values
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= xFifoRegisterAddress;
|
||
|
|
registerDataOut <= 16#4000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= -16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= -16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= 16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for 10*registerWriteDelay;
|
||
|
|
-- write Y FIFO values
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= yFifoRegisterAddress;
|
||
|
|
registerDataOut <= -16#4000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= 16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= 16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
registerDataOut <= -16#7000#;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for 10*registerWriteDelay;
|
||
|
|
-- end pattern update and start run
|
||
|
|
patternLength <= 4;
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= controlRegisterAddress;
|
||
|
|
registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb);
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
-- set lower speed execution
|
||
|
|
updatePeriod <= 9;
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
registerAddress <= speedRegisterAddress;
|
||
|
|
registerDataOut <= updatePeriod;
|
||
|
|
registerWrite <= '1', '0' after clockPeriod;
|
||
|
|
wait for registerWriteDelay;
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
-- sin/cos debug mode
|
||
|
|
wait for 700 us - now;
|
||
|
|
testInformation <= pad("Drawing debug mode circle", testInformation'length);
|
||
|
|
wait for 0 ns;
|
||
|
|
print(testSeparator & cr & testInformation);
|
||
|
|
selSinCos <= '1';
|
||
|
|
----------------------------------------------------------------------------
|
||
|
|
-- stop simulation
|
||
|
|
wait for 1 ms - now;
|
||
|
|
assert false
|
||
|
|
report "End" & cr & " --> " &
|
||
|
|
"End of simulation"
|
||
|
|
severity failure;
|
||
|
|
end process testSequence;
|
||
|
|
|
||
|
|
------------------------------------------------------------------------------
|
||
|
|
-- AMBA bus access
|
||
|
|
busAccess: process
|
||
|
|
variable writeAccess: boolean;
|
||
|
|
variable hRData01: std_ulogic_vector(hRData'range);
|
||
|
|
begin
|
||
|
|
hAddr <= (others => '-');
|
||
|
|
hWData <= (others => '-');
|
||
|
|
hTrans <= transIdle;
|
||
|
|
hSel <= '0';
|
||
|
|
hWrite <= '0';
|
||
|
|
wait on registerWrite, registerRead;
|
||
|
|
writeAccess := false;
|
||
|
|
if rising_edge(registerWrite) then
|
||
|
|
writeAccess := true;
|
||
|
|
end if;
|
||
|
|
-- phase 1: address and controls
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
hAddr <= to_unsigned(registerAddress, hAddr'length);
|
||
|
|
hTrans <= transNonSeq;
|
||
|
|
hSel <= '1';
|
||
|
|
if writeAccess then
|
||
|
|
hWrite <= '1';
|
||
|
|
end if;
|
||
|
|
-- phase 2: data
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
hAddr <= (others => '-');
|
||
|
|
hTrans <= transIdle;
|
||
|
|
hSel <= '0';
|
||
|
|
hWrite <= '0';
|
||
|
|
if writeAccess then
|
||
|
|
hWData <= std_uLogic_vector(to_signed(registerDataOut, hWData'length));
|
||
|
|
else
|
||
|
|
wait until falling_edge(clock_int);
|
||
|
|
hRData01 := hRData;
|
||
|
|
for index in hRData01'range loop
|
||
|
|
if (hRData01(index) /= '0') and (hRData01(index) /= '1') then
|
||
|
|
hRData01(index) := '0';
|
||
|
|
end if;
|
||
|
|
end loop;
|
||
|
|
registerDataIn <= to_integer(unsigned(hRData01));
|
||
|
|
end if;
|
||
|
|
wait until rising_edge(clock_int);
|
||
|
|
end process;
|
||
|
|
|
||
|
|
END ARCHITECTURE test;
|