91 lines
2.7 KiB
VHDL
91 lines
2.7 KiB
VHDL
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-- filename: toggler.vhd
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-- kind: vhdl file
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-- first created: 05.03.2012
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-- created by: zas
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--------------------------------------------------------------------------------
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-- History:
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-- v0.1 : cof 22.01.2013 -- Initial version
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--------------------------------------------------------------------------------
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-- Description:
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-- Debounces a button on both edges.
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-- _ _
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-- input ____/ \__________________________/ \____________
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-- _____________________________
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-- output _____/ \____________
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--
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-- If the generic "counterBitNb" is greater than zero, a debouncer is placed on
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-- the input signal.
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--
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--------------------------------------------------------------------------------
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ARCHITECTURE rtl OF toggler IS
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signal inputDebounced : std_ulogic;
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signal inputDelayed, inputChangedTo1 : std_ulogic;
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signal toggle_int : std_ulogic;
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COMPONENT debouncer
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GENERIC (
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counterBitNb : positive := 18;
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invertInput : std_ulogic := '0'
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);
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PORT (
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reset : IN std_ulogic ;
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clock : IN std_ulogic ;
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input : IN std_ulogic ;
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debounced : OUT std_ulogic
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);
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END COMPONENT;
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BEGIN
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------------------------------------------------------------------------------
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-- Debounce input
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useInputDirectly: if counterBitNb = 0 generate
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inputDebounced <= input;
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end generate useInputDirectly;
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debounceInput: if counterBitNb > 0 generate
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I_debouncer : debouncer
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GENERIC MAP (
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counterBitNb => counterBitNb,
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invertInput => invertInput
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)
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PORT MAP (
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reset => reset,
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clock => clock,
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input => input,
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debounced => inputDebounced
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);
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end generate debounceInput;
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------------------------------------------------------------------------------
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-- Find edge on input
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delayInput: process(reset, clock)
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begin
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if reset = '1' then
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inputDelayed <= '0';
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elsif rising_edge(clock) then
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inputDelayed <= inputDebounced;
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end if;
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end process delayInput;
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inputChangedTo1 <= '1' when (inputDebounced = '1') and (inputDelayed = '0')
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else '0';
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------------------------------------------------------------------------------
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-- Toggle output
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toggleOutput: process(reset, clock)
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begin
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if reset = '1' then
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toggle_int <= '0';
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elsif rising_edge(clock) then
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if inputChangedTo1 = '1' then
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toggle_int <= not toggle_int;
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end if;
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end if;
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end process toggleOutput;
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toggle <= toggle_int;
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END ARCHITECTURE rtl;
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