28 lines
1012 B
VHDL
28 lines
1012 B
VHDL
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-- Allows to use RGB pins from ice40 FPGAs
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-- as user I/Os
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library sb_ice40_components_syn;
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use sb_ice40_components_syn.components.all;
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ARCHITECTURE rtl OF ice40_sbIoOd IS
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BEGIN
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ODInst : SB_IO_OD
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generic map (
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NEG_TRIGGER => '0', -- FF's are rising edge
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PIN_TYPE => "011001" -- 0110 = PIN_OUT, 01 = PIN_INPUT
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)
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port map (
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DOUT1 => open, -- Output on falling edge
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DOUT0 => '1', -- Output on rising edge
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CLOCKENABLE => '1', -- Clock Enable common to input and output clocks
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LATCHINPUTVALUE => '0', -- Not latching input value
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INPUTCLK => clk, -- Clock for the input registers
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DIN1 => open, -- Input on falling edge
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DIN0 => rgbRd, -- Input value
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OUTPUTENABLE => rgbWr, -- Output Pin Tristate/Enable control
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OUTPUTCLK => clk, -- Clock for the output registers
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PACKAGEPIN => rgbPin -- User’s Pin signal name
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);
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END ARCHITECTURE rtl;
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