71 lines
2.6 KiB
VHDL
71 lines
2.6 KiB
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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library ECP5U;
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use ECP5U.components.all;
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ENTITY pll_vga IS
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PORT(
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clkIn100M : IN std_ulogic;
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clk25MHz : OUT std_ulogic;
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pllLocked : OUT std_ulogic
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);
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-- Declarations
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END pll_vga ;
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architecture Structure of pll_vga is
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-- internal signal declarations
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signal REFCLK: std_logic;
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signal CLKOP_t: std_logic;
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signal CLKFB_t: std_logic;
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signal scuba_vhi: std_logic;
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signal scuba_vlo: std_logic;
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attribute FREQUENCY_PIN_CLKOP : string;
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attribute FREQUENCY_PIN_CLKI : string;
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attribute ICP_CURRENT : string;
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attribute LPF_RESISTOR : string;
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "25.000000";
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attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
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attribute ICP_CURRENT of PLLInst_0 : label is "6";
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attribute LPF_RESISTOR of PLLInst_0 : label is "16";
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of Structure : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vhi_inst: VHI
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port map (Z=>scuba_vhi);
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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PLLInst_0: EHXPLLL
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generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
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STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
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CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
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CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
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CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 25, PLL_LOCK_MODE=> 0,
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CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
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CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
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OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
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CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 26, CLKFB_DIV=> 1,
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CLKI_DIV=> 4, FEEDBK_PATH=> "INT_OP")
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port map (CLKI=>clkIn100M, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
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PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
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PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
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STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
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ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
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ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
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CLKOS2=>open, CLKOS3=>open, LOCK=>pllLocked, INTLOCK=>open,
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REFCLK=>REFCLK, CLKINTFB=>CLKFB_t);
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clk25MHz <= CLKOP_t;
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end Structure;
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